AT91SAM9261-CJ

AT91SAM9261-CJ Datasheet

AT91 ARM Thumb-based Microcontrollers AT91SAM9261 Preliminary Summary

Part	Datasheet
AT91SAM9261-CJ	AT91SAM9261-CJ (pdf)

Related Parts	Information
AT91SAM9261B-CU	AT91SAM9261B-CU
AT91SAM9261-CJ-999	AT91SAM9261-CJ-999

PDF Datasheet Preview
• Incorporates the ARM926EJ-S Processor DSP Instruction Extensions ARM Technology for Acceleration 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer 210 MIPS at 190 MHz Memory Management Unit EmbeddedICE , Debug Communication Channel Support Mid-level implementation Embedded Trace Macrocell • Additional Embedded Memories 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed • External Bus Interface EBI Supports SDRAM, Static Memory, NAND Flash and • LCD Controller Supports Passive or Active Displays Up to 16-bits per Pixel in STN Color Mode Up to 16M Colors in TFT Mode 24-bit per Pixel , Resolution up to 2048 x 2048 • USB Full Speed 12 Mbits per second Host Double Port • Dual On-chip Transceivers • Integrated FIFOs and Dedicated DMA Channels USB Full Speed 12 Mbits per second Device Port • On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs • Bus Matrix Handles Five Masters and Five Slaves Boot Mode Select Option Remap Command • Fully Featured System Controller SYSC for Efficient System Management, including Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes Clock Generator and Power Management Controller Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real-time Timer Three 32-bit PIO Controllers • Reset Controller RSTC Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control • Shutdown Controller SHDWC Programmable Shutdown Pin Control and Wake-up Circuitry • Clock Generator CKGR 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock 3 to 20 MHz On-chip Oscillator and two PLLs • Power Management Controller PMC Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Signals AT91 ARM Thumb-based Microcontrollers AT91SAM9261 Preliminary Summary NOTE This is a summary document. The complete document is available on the Atmel website at • Advanced Interrupt Controller AIC Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected • Debug Unit DBGU 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention Mode for General Purpose Two-wire UART Serial Communication • Periodic Interval Timer PIT 20-bit Interval Timer plus 12-bit Interval Counter • Watchdog Timer WDT Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock • Real-Time Timer RTT 32-bit Free-running Backup Counter Running at Slow Clock • Three 32-bit Parallel Input/Output Controllers PIO PIOA, PIOB and PIOC 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os Input Change Interrupt Capability on Each I/O Line Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output • Nineteen Peripheral DMA PDC Channels • Multimedia Card Interface MCI SDCard and MultiMediaCard Compliant Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant • Three Synchronous Serial Controllers SSC Independent Clock and Frame Sync Signals for Each Receiver and Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer • Three Universal Synchronous/Asynchronous Receiver Transmitters USART Individual Baud Rate Generator, Infrared Modulation/Demodulation Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support • Two Master/Slave Serial Peripheral Interface SPI 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects • One Three-channel 16-bit Timer/Counters TC Three External Clock Inputs, Two multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • Two-wire Interface TWI Master Mode Support, All Two-wire Atmel EEPROMs Supported • JTAG Boundary Scan on All Digital Pins • Required Power Supplies 1.08V to 1.32V for VDDCORE and VDDBU 3.0V to 3.6V for VDDOSC and for VDDPLL 2.7V to 3.6V for VDDIOP Peripheral I/Os 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM Memory I/Os • Available in a 217-ball LFBGA RoHS-compliant Package 2 AT91SAM9261 Preliminary AT91SAM9261 Preliminary The AT91SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM SDRAM and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The AT91SAM9261 integrates a ROM-based Boot Loader supporting code shadowing from, for example, external into external SDRAM. The software controlled Power Management Controller PMC keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency. The AT91SAM9261 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel DBGU and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints. Block Diagram Figure AT91SAM9261 Block Diagram JTAGSEL TDI TDO TMS TCK NTRST RTCK TST FIQ IRQ0-IRQ2 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XIN XOUT XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST MCCK MCCDA MCDA0-MCDA3 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK JTAG Boundary Scan Ordering Information Table AT91SAM9261 Ordering Information Ordering Code Package AT91SAM9261-CJ BGA217 AT91SAM9261B-CU BGA217 Package Type RoHS-compliant Green Temperature Operating Range Industrial -40°C to 85°C Industrial -40°C to 85°C 40 AT91SAM9261 Preliminary AT91SAM9261 Preliminary Source Comments 6062AS Qualified/Internal 23-Aug-04 Date 02-Jun-05 CSR 04-370 Change to Additional Embedded Memories in “Features” on page Change to Section “Power Consumption” on page Change to Table 8-3 on page CSR 04-371 Change to AIC, “Features” on page 1, SMCS signal added to Table 3-1, “Signal Description by Peripheral,” on page 5, Change to Section “NAND Flash Interface” on page CSR 04-376 Added NTRST signal to“Block Diagram” on page NTRST signal added to Table 3-1 on page F1 modified in Table 4-1 on page Change to “JTAG Port Pins” on page CSR 04-446 Changed ROM access to single cycle in “Features” on page 1 and Section “Embedded Memories” on page CSR 04-447 Replaced “PDMA” with “PDC” throughout. Replaced “Peripheral DMA” with “Peripheral DMA Controller” throughout. CSR 04-461 New pinout for 217-ball LFBGA package, Table 2 updated. 6062BS CSR 04-475 CSR 05-023 Updated Section ”Boot Program” on page Removed “Embedded Software Services” on page Changed min voltage level for VDDIOM and VDDIOP to 2.7V throughout. Corrected nominal voltage level for VDDIOP and VDDIOP in Section “Power Supplies” on page CSR 05-024 Added information on chip select assignment management in Section “External Bus Interface” on page Added information on configuration management of embedded pad pull-up in Section “USB” on page Throughout document All references to SmartMedia removed and replaced by NAND Flash. All signals SMxx changed to NANDxx. Throughout document Package now qualified as RoHS-compliant Changed pull-up resistor level to 10 kOhm in Section “PIO Controller A, B and C Lines” on page Changed typical conditions for VDDCORE to 1.2V in Section “Power Consumption” on page CSR 05-487 Updated Table 12-1, “AT91SAM9261 Ordering Information,” on page 6062ES 6062FS 6062GS 6062HS Source 2292 2946 2475 2474 2480 3068 3147 3067 3503 3660, 3695 3660 3491 5042 Comments Corrected MIPS and speed on page Added information on EBI NCS0 hwhen BMS = 0 in Table 8-3, “Internal Memory Mapping,” on page Updated information on JTAGSEL in Section 3-1 “Signal Description by Peripheral” on page 5 and in Section “JTAG Port Pins” on page Reformatted Section “Memories” on page Inserted new Figure 8-1, “AT91SAM9261 Memory Mapping,” on page 16 to show full product memory mapping. Removed information on Timer Counter clock assignments in Section “Timer Counter” on page Inserted new Section “Boot Strategies” on page 20 to replace Boot ROM section. Changed pin name for ball D9 to SHDN in Table 4-1, “AT91SAM9261 Pinout for 217-ball LFBGA Package 1 ,” on page Updated information on shutdown pin in Section “Shutdown Logic Pins” on page Updated peripheral mnemonics in Figure 8-1, “AT91SAM9261 Memory Mapping,” on page Added note to Table 10-1, “Peripheral Identifiers,” on page Updated VDDOSC, VDDPLL and VDDIOM ranges in”Features”, Table 3-1, “Signal Description by Peripheral,” on page 5 and Section “Power Consumption” on page Added ROM to Figure 8-1, “AT91SAM9261 Memory Mapping,” on page Updated Section “Power Management Controller” on page 25 and Figure 9-3, “Power Management Controller Block Diagram,” on page Added Section “Package Drawing” on page Table 10-4, “Multiplexing on PIO Controller C,” on page 33, PCO - PC7 and PC12-PC13 power supplies are VDDIOP not VDDIOM. Table 10-2, “Multiplexing on PIO Controller A,” on page 31 PA30-PA31 power supplies are VDDIOP not VDDIOM 6062IS 6062JS 5027 rfo 4965 4844 4835 4241 5250 5248 Section “Boot Strategies”, removed sentence pertaining to “remap” Section “BMS = 1, Boot on Embedded ROM”, added NANDFlash Boot. Section “Power Supplies”, startup voltage slope requirements for VDDCORE and VDDBU added. Table 10-3, “Multiplexing on PIO Controller B,” on page 32, Note added to “PB3” comments Figure 9-3, “Power Management Controller Block Diagram,” on page 25, in the master memory controller representation, the divider has been updated. Table 4-1 on page 10, PCO - PC7, PC8 - PC11, PC12 - PC15 power supplies are VDDIOP not VDDIOM. Section “Power Consumption”, startup voltage slope requirements for VDDCORE and VDDBU removed. In Features, on page 2 Required Power Supply updated, 3.0V to 3.6V for VDDOSC and for VDDPLL 42 AT91SAM9261 Preliminary AT91SAM9261 Preliminary Source Comments 6062KS 5846 5932 In Features, on page 2 Debug Unit DBGU updated Section “USART”, manchester encoding option is not avaiilable. Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support AT91SAM Support Atmel techincal support Sales Contacts Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2009 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others are registered trademarks and others are trademarks of Atmel Corporation or its subsidiaries. the logo, and others are the registered trademarks or trademarks of ARM Ltd. and others are the registered trademarks or trademarks of Microsoft Corporation in the US and/or other countries. Other terms and product names may be the trademarks of others.

PDF Datasheet Preview

• Incorporates the ARM926EJ-S Processor DSP Instruction Extensions ARM Technology for Acceleration 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer 210 MIPS at 190 MHz Memory Management Unit EmbeddedICE , Debug Communication Channel Support Mid-level implementation Embedded Trace Macrocell
• Additional Embedded Memories 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed
• External Bus Interface EBI Supports SDRAM, Static Memory, NAND Flash and
• LCD Controller Supports Passive or Active Displays Up to 16-bits per Pixel in STN Color Mode Up to 16M Colors in TFT Mode 24-bit per Pixel , Resolution up to 2048 x 2048
• USB Full Speed 12 Mbits per second Host Double Port
• Dual On-chip Transceivers
• Integrated FIFOs and Dedicated DMA Channels USB Full Speed 12 Mbits per second Device Port
• On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs
• Bus Matrix Handles Five Masters and Five Slaves Boot Mode Select Option Remap Command
• Fully Featured System Controller SYSC for Efficient System Management, including Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes Clock Generator and Power Management Controller Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real-time Timer Three 32-bit PIO Controllers
• Reset Controller RSTC Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control
• Shutdown Controller SHDWC Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator CKGR 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock 3 to 20 MHz On-chip Oscillator and two PLLs
• Power Management Controller PMC Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Signals

AT91 ARM Thumb-based Microcontrollers AT91SAM9261 Preliminary Summary

NOTE This is a summary document. The complete document is available on the Atmel website at
• Advanced Interrupt Controller AIC Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit DBGU 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention Mode for General Purpose Two-wire UART Serial Communication
• Periodic Interval Timer PIT 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer WDT Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock
• Real-Time Timer RTT 32-bit Free-running Backup Counter Running at Slow Clock
• Three 32-bit Parallel Input/Output Controllers PIO PIOA, PIOB and PIOC 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os Input Change Interrupt Capability on Each I/O Line Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Nineteen Peripheral DMA PDC Channels
• Multimedia Card Interface MCI

SDCard and MultiMediaCard Compliant Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant
• Three Synchronous Serial Controllers SSC Independent Clock and Frame Sync Signals for Each Receiver and Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Three Universal Synchronous/Asynchronous Receiver Transmitters USART Individual Baud Rate Generator, Infrared Modulation/Demodulation Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
• Two Master/Slave Serial Peripheral Interface SPI 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counters TC Three External Clock Inputs, Two multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• Two-wire Interface TWI Master Mode Support, All Two-wire Atmel EEPROMs Supported
• JTAG Boundary Scan on All Digital Pins
• Required Power Supplies 1.08V to 1.32V for VDDCORE and VDDBU 3.0V to 3.6V for VDDOSC and for VDDPLL 2.7V to 3.6V for VDDIOP Peripheral I/Os 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM Memory I/Os
• Available in a 217-ball LFBGA RoHS-compliant Package
2 AT91SAM9261 Preliminary

AT91SAM9261 Preliminary

The AT91SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM SDRAM and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The AT91SAM9261 integrates a ROM-based Boot Loader supporting code shadowing from, for example, external into external SDRAM. The software controlled Power Management Controller PMC keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency. The AT91SAM9261 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel DBGU and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints.

Block Diagram

Figure AT91SAM9261 Block Diagram

JTAGSEL TDI TDO TMS TCK

NTRST RTCK

TST FIQ IRQ0-IRQ2 DRXD DTXD PCK0-PCK3

PLLRCA PLLRCB

XIN XOUT

XIN32 XOUT32

SHDN WKUP

VDDBU GNDBU

VDDCORE NRST

MCCK MCCDA MCDA0-MCDA3

RXD0 TXD0 SCK0 RTS0 CTS0

RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2

SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3

SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK

JTAG Boundary Scan
Ordering Information
Table AT91SAM9261 Ordering Information
Ordering Code

Package

AT91SAM9261-CJ

BGA217

AT91SAM9261B-CU

BGA217

Package Type RoHS-compliant

Green

Temperature Operating Range

Industrial -40°C to 85°C

Industrial -40°C to 85°C
40 AT91SAM9261 Preliminary

AT91SAM9261 Preliminary

Source

Comments
6062AS

Qualified/Internal 23-Aug-04

Date 02-Jun-05

CSR 04-370

Change to Additional Embedded Memories in “Features” on page Change to Section “Power Consumption” on page Change to Table 8-3 on page

CSR 04-371

Change to AIC, “Features” on page 1, SMCS signal added to Table 3-1, “Signal Description by Peripheral,” on page 5, Change to Section “NAND Flash Interface” on page

CSR 04-376

Added NTRST signal to“Block Diagram” on page NTRST signal added to Table 3-1 on page F1 modified in Table 4-1 on page Change to “JTAG Port Pins” on page

CSR 04-446

Changed ROM access to single cycle in “Features” on page 1 and Section “Embedded Memories” on page

CSR 04-447

Replaced “PDMA” with “PDC” throughout. Replaced “Peripheral DMA” with “Peripheral DMA Controller” throughout.

CSR 04-461 New pinout for 217-ball LFBGA package, Table 2 updated.
6062BS

CSR 04-475 CSR 05-023

Updated Section ”Boot Program” on page

Removed “Embedded Software Services” on page

Changed min voltage level for VDDIOM and VDDIOP to 2.7V throughout. Corrected nominal voltage level for VDDIOP and VDDIOP in Section “Power Supplies” on page

CSR 05-024

Added information on chip select assignment management in Section “External Bus Interface” on page

Added information on configuration management of embedded pad pull-up in Section “USB” on page

Throughout document All references to SmartMedia removed and replaced by NAND Flash. All signals SMxx changed to NANDxx.

Throughout document Package now qualified as RoHS-compliant

Changed pull-up resistor level to 10 kOhm in Section “PIO Controller A, B and C Lines” on page

Changed typical conditions for VDDCORE to 1.2V in Section “Power Consumption” on page
CSR 05-487 Updated Table 12-1, “AT91SAM9261 Ordering Information,” on page
6062ES
6062FS
6062GS 6062HS

Source
2292 2946 2475 2474 2480 3068 3147 3067 3503 3660, 3695 3660 3491
5042

Comments

Corrected MIPS and speed on page

Added information on EBI NCS0 hwhen BMS = 0 in Table 8-3, “Internal Memory Mapping,” on page

Updated information on JTAGSEL in Section 3-1 “Signal Description by Peripheral” on page 5 and in Section “JTAG Port Pins” on page

Reformatted Section “Memories” on page Inserted new Figure 8-1, “AT91SAM9261 Memory Mapping,” on page 16 to show full product memory mapping.

Removed information on Timer Counter clock assignments in Section “Timer Counter” on page

Inserted new Section “Boot Strategies” on page 20 to replace Boot ROM section.

Changed pin name for ball D9 to SHDN in Table 4-1, “AT91SAM9261 Pinout for 217-ball LFBGA Package 1 ,” on page

Updated information on shutdown pin in Section “Shutdown Logic Pins” on page

Updated peripheral mnemonics in Figure 8-1, “AT91SAM9261 Memory Mapping,” on page

Added note to Table 10-1, “Peripheral Identifiers,” on page

Updated VDDOSC, VDDPLL and VDDIOM ranges in”Features”, Table 3-1, “Signal Description by Peripheral,” on page 5 and Section “Power Consumption” on page

Added ROM to Figure 8-1, “AT91SAM9261 Memory Mapping,” on page

Updated Section “Power Management Controller” on page 25 and Figure 9-3, “Power Management Controller Block Diagram,” on page

Added Section “Package Drawing” on page

Table 10-4, “Multiplexing on PIO Controller C,” on page 33, PCO - PC7 and PC12-PC13 power supplies are VDDIOP not VDDIOM. Table 10-2, “Multiplexing on PIO Controller A,” on page 31 PA30-PA31 power supplies are VDDIOP not VDDIOM
6062IS 6062JS
5027 rfo 4965 4844 4835
4241
5250 5248

Section “Boot Strategies”, removed sentence pertaining to “remap” Section “BMS = 1, Boot on Embedded ROM”, added NANDFlash Boot.

Section “Power Supplies”, startup voltage slope requirements for VDDCORE and VDDBU added.

Table 10-3, “Multiplexing on PIO Controller B,” on page 32, Note added to “PB3” comments

Figure 9-3, “Power Management Controller Block Diagram,” on page 25, in the master memory controller representation, the divider has been updated.

Table 4-1 on page 10, PCO - PC7, PC8 - PC11, PC12 - PC15 power supplies are VDDIOP not VDDIOM.

Section “Power Consumption”, startup voltage slope requirements for VDDCORE and VDDBU removed.

In Features, on page 2 Required Power Supply updated, 3.0V to 3.6V for VDDOSC and for VDDPLL
42 AT91SAM9261 Preliminary

AT91SAM9261 Preliminary

Source

Comments
6062KS
5846 5932

In Features, on page 2 Debug Unit DBGU updated Section “USART”, manchester encoding option is not avaiilable.
Headquarters

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600

International

Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369

Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Product Contact

Web Site

Literature Requests

Technical Support AT91SAM Support Atmel techincal support

Sales Contacts

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
2009 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others are registered trademarks and others are trademarks of Atmel Corporation or its subsidiaries. the logo, and others are the registered trademarks or trademarks of ARM Ltd. and others are the registered trademarks or trademarks of Microsoft Corporation in the US and/or other countries. Other terms and product names may be the trademarks of others.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT91SAM9261-CJ Datasheet file may be downloaded here without warranties.

Datasheet ID: AT91SAM9261-CJ 519135