AT91M55800-33AI

AT91M55800-33AI Datasheet

AT91 Microcontrollers

Part	Datasheet
AT91M55800-33AI	AT91M55800-33AI (pdf)

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• Utilizes the ARM7TDMI ARM Thumb Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt Embedded ICE In-Circuit Emulation • 8K Bytes Internal SRAM • Fully-programmable External Bus Interface EBI Maximum External Address Space of 128M Bytes 8 Chip Selects Software Programmable 8/16-bit External Databus • 8-level Priority, Individually Maskable, Vectored Interrupt Controller 7 External Interrupts, Including a High-priority, Low-latency Interrupt Request • 58 Programmable I/O Lines • 6-channel 16-bit Timer/Counter 6 External Clock Inputs and 2 Multi-purpose I/O Pins per Channel • 3 USARTs • Master/Slave SPI Interface 8-bit to 16-bit Programmable Data Length 4 External Slave Chip Selects • Programmable Watchdog Timer • 8-channel 10-bit ADC • 2-channel 10-bit DAC • Clock Generator with On-chip Main Oscillator and PLL for Multiplication 3 to 20 MHz Frequency Range Main Oscillator • Real-time Clock with On-chip 32 kHz Oscillator Battery Backup Operation and External Alarm • 8-channel Peripheral Data Controller for USARTs and SPIs • Advanced Power Management Controller APMC Normal, Wait, Slow, Standby and Power-down modes • IEEE JTAG Boundary-scan on all Digital Pins • Fully Static Operation 0 Hz to 33 MHz Internal Frequency Range at VDDCORE = 3.0V, 85°C • 2.7V to 3.6V Core Operating Range, 2.7V to 5.5V I/O Operating Range • 2.7V to 3.6V Analog Operating Range • 1.8V to 3.6V Backup Battery Operating Range • 2.7V to 3.6V Oscillator and PLL Operating Range • -40°C to +85°C Temperature Range • Available in a 176-lead TQFP or 176-ball BGA Package AT91 Microcontrollers AT91M55800A Summary The AT91M55800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The fully programmable External Bus Interface provides a direct connection to off-chip memory in as fast as one clock cycle for a read or write operation. An eight-level priority vectored interrupt controller in conjunction with the peripheral data controller significantly improve the real-time performance of the device. The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip SRAM, a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic chip, the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and costeffective solution to many ultra low-power applications. Note This is a summary document. A complete document is available on our web site at Pin Configurations Table Pin Configuration for 176-lead TQFP Package Pin AT91M55800A Pin AT91M55800A NCS0 NCS1 NCS2 NCS3 NLB/A0 PB19/TCLK0 PB20/TIOA0 PB21/TIOB0 PB22/TCLK1 VDDIO VDDIO PB23/TIOA1 PB24/TIOB1 PB25/TCLK2 PB26/TIOA2 PB27/TIOB2 PA0/TCLK3 Product overview Ordering information Packaging information Soldering profile Document Title ARM7TDMI Thumb Datasheet AT91M55800A Datasheet AT91M55800A Electrical Characteristics AT91M55800A Summary Datasheet this document Product Overview Power Supplies Input/Output Considerations The AT91M55800A has 5 kinds of power supply pins • VDDCORE pins, which power the chip core • VDDIO pins, which power the I/O Lines • VDDPLL pins, which power the oscillator and PLL cells • VDDA pins, which power the analog peripherals ADC and DAC • VDDBU pins, which power the RTC, the 32768 Hz oscillator and the Shut-down Logic of the APMC VDDIO and VDDCORE are separated to permit the I/O lines to be powered with 5V, thus resulting in full TTL compliance. The following ground pins are provided • GND for both VDDCORE and VDDIO • GNDPLL for VDDPLL • GNDA for VDDA • GNDBU for VDDBU All of these ground pins must be connected to the same voltage generally the board electric ground with wires as short as possible. GNDPLL, GNDA and GNDBU are provided separately in order to allow the user to add a decoupling capacitor directly between the power and ground pads. In the same way, the PLL filter resistor and capacitors must be connected to the device and to GNDBU with wires as short as possible. Also, the external load capacitances of the main oscillator crystal and the 32768 Hz crystal must be connected respectively to GNDPLL and to GNDBU with wires as short as possible. The main constraints applying to the different voltages of the device are • VDDBU must be lower than or equal to VDDCORE • VDDA must be higher than or equal to VDDCORE • VDDCORE must be lower than or equal to VDDIO The nominal power combinations supported by the AT91M55800A are described in the following table: Table Nominal Power Combinations VDDIO VDDCOR E VDDA VDDPLL VDDBU Maximum Operating Frequency 33 MHz 3.3V 3.3V 3.3V 3.3V 3.3V 33 MHz 3.3V 3.3V 3.3V 3.3V 33 MHz After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the AT91M55800A microcontroller be held at valid logic levels to minimize the power consumption. 12 AT91M55800A AT91M55800A Master Clock Reset NRST Pin Watchdog Reset Emulation Functions Tri-state Mode JTAG/ICE Debug Mode Master Clock is generated in one of the following ways, depending on programming in the APMC registers • From the 32768 Hz low-power oscillator that clocks the RTC • The on-chip main oscillator, together with a PLL, generate a software-programmable Ordering Information Table Ordering Information Ordering Code AT91M55800A-33AI AT91M55800A-33CI Package TQFP 176 BGA 176 AT91M55800A Temperature Operating Range Industrial -40°C to 85°C Packaging Information Figure 176-lead Thin Quad Flat Pack Package Drawing PIN 1 20 AT91M55800A AT91M55800A Table Common Dimensions mm 11° 12° 13° 11° 12° 13° Tolerances of form and position Table Lead Count Dimensions mm D1/E1 Count BSC Table Device and 176-lead TQFP Package Maximum Weight 2023 Figure 176-ball Grid Array Package Drawing Top View Bottom View Symbol aaa bbb ddd eee fff ggg hhh kkk Maximum Package dimensions conform to JEDEC MO-205 Dimensioning and tolerancing per ASME Y14.5M-1994 All dimensions in mm Solder Ball position designation per JESD 95-1, SPP-010 Primary datum Z and seating plane are defined by the spherical crowns of the solder balls Table Device and 176-ball BGA Package Maximum Weight 22 AT91M55800A Soldering Profile AT91M55800A Table 12 gives the recommended soldering profile from J-STD-20. Table Soldering Profile Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature

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• Utilizes the ARM7TDMI ARM Thumb Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set

Leader in MIPS/Watt

Embedded ICE In-Circuit Emulation
• 8K Bytes Internal SRAM
• Fully-programmable External Bus Interface EBI

Maximum External Address Space of 128M Bytes 8 Chip Selects

Software Programmable 8/16-bit External Databus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
7 External Interrupts, Including a High-priority, Low-latency Interrupt Request
• 58 Programmable I/O Lines
• 6-channel 16-bit Timer/Counter
6 External Clock Inputs and 2 Multi-purpose I/O Pins per Channel
• 3 USARTs
• Master/Slave SPI Interface
8-bit to 16-bit Programmable Data Length
4 External Slave Chip Selects
• Programmable Watchdog Timer
• 8-channel 10-bit ADC
• 2-channel 10-bit DAC
• Clock Generator with On-chip Main Oscillator and PLL for Multiplication
3 to 20 MHz Frequency Range Main Oscillator
• Real-time Clock with On-chip 32 kHz Oscillator

Battery Backup Operation and External Alarm
• 8-channel Peripheral Data Controller for USARTs and SPIs
• Advanced Power Management Controller APMC

Normal, Wait, Slow, Standby and Power-down modes
• IEEE JTAG Boundary-scan on all Digital Pins
• Fully Static Operation 0 Hz to 33 MHz Internal Frequency Range
at VDDCORE = 3.0V, 85°C
• 2.7V to 3.6V Core Operating Range, 2.7V to 5.5V I/O Operating Range
• 2.7V to 3.6V Analog Operating Range
• 1.8V to 3.6V Backup Battery Operating Range
• 2.7V to 3.6V Oscillator and PLL Operating Range
• -40°C to +85°C Temperature Range
• Available in a 176-lead TQFP or 176-ball BGA Package

AT91 Microcontrollers

AT91M55800A Summary

The AT91M55800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications.

The fully programmable External Bus Interface provides a direct connection to off-chip memory in as fast as one clock cycle for a read or write operation. An eight-level priority vectored interrupt controller in conjunction with the peripheral data controller significantly improve the real-time performance of the device.

The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip SRAM, a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic chip, the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and costeffective solution to many ultra low-power applications.

Note This is a summary document. A complete document
is available on our web site at

Pin Configurations

Table Pin Configuration for 176-lead TQFP Package

Pin AT91M55800A

Pin AT91M55800A

NCS0

NCS1

NCS2

NCS3

NLB/A0

PB19/TCLK0

PB20/TIOA0

PB21/TIOB0

PB22/TCLK1

VDDIO

VDDIO

PB23/TIOA1

PB24/TIOB1

PB25/TCLK2

PB26/TIOA2

PB27/TIOB2

PA0/TCLK3
Product overview Ordering information Packaging information Soldering profile

Document Title ARM7TDMI Thumb Datasheet AT91M55800A Datasheet AT91M55800A Electrical Characteristics

AT91M55800A Summary Datasheet this document

Product Overview

Power Supplies

Input/Output Considerations

The AT91M55800A has 5 kinds of power supply pins
• VDDCORE pins, which power the chip core
• VDDIO pins, which power the I/O Lines
• VDDPLL pins, which power the oscillator and PLL cells
• VDDA pins, which power the analog peripherals ADC and DAC
• VDDBU pins, which power the RTC, the 32768 Hz oscillator and the Shut-down

Logic of the APMC

VDDIO and VDDCORE are separated to permit the I/O lines to be powered with 5V, thus resulting in full TTL compliance.

The following ground pins are provided
• GND for both VDDCORE and VDDIO
• GNDPLL for VDDPLL
• GNDA for VDDA
• GNDBU for VDDBU

All of these ground pins must be connected to the same voltage generally the board electric ground with wires as short as possible. GNDPLL, GNDA and GNDBU are provided separately in order to allow the user to add a decoupling capacitor directly between the power and ground pads. In the same way, the PLL filter resistor and capacitors must be connected to the device and to GNDBU with wires as short as possible. Also, the external load capacitances of the main oscillator crystal and the 32768 Hz crystal must be connected respectively to GNDPLL and to GNDBU with wires as short as possible.

The main constraints applying to the different voltages of the device are
• VDDBU must be lower than or equal to VDDCORE
• VDDA must be higher than or equal to VDDCORE
• VDDCORE must be lower than or equal to VDDIO

The nominal power combinations supported by the AT91M55800A are described in the following table:

Table Nominal Power Combinations

VDDIO

VDDCOR E

VDDA

VDDPLL VDDBU

Maximum Operating Frequency
33 MHz
3.3V
3.3V
3.3V
3.3V
3.3V
33 MHz
3.3V
3.3V
3.3V
3.3V
33 MHz

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the AT91M55800A microcontroller be held at valid logic levels to minimize the power consumption.
12 AT91M55800A

AT91M55800A

Master Clock

Reset

NRST Pin Watchdog Reset

Emulation Functions

Tri-state Mode

JTAG/ICE Debug Mode

Master Clock is generated in one of the following ways, depending on programming in the APMC registers
• From the 32768 Hz low-power oscillator that clocks the RTC
• The on-chip main oscillator, together with a PLL, generate a software-programmable
Ordering Information
Table Ordering Information
Ordering Code AT91M55800A-33AI AT91M55800A-33CI

Package TQFP 176 BGA 176

AT91M55800A

Temperature Operating Range

Industrial -40°C to 85°C

Packaging Information

Figure 176-lead Thin Quad Flat Pack Package Drawing

PIN 1
20 AT91M55800A

AT91M55800A

Table Common Dimensions mm
11°
12°
13°
11°
12°
13°

Tolerances of form and position

Table Lead Count Dimensions mm

D1/E1

Count BSC

Table Device and 176-lead TQFP Package Maximum Weight
2023

Figure 176-ball Grid Array Package Drawing

Top View

Bottom View

Symbol aaa bbb ddd eee fff ggg hhh kkk

Maximum

Package dimensions conform to JEDEC MO-205

Dimensioning and tolerancing per ASME Y14.5M-1994

All dimensions in mm Solder Ball position designation
per JESD 95-1, SPP-010 Primary datum Z and seating
plane are defined by the spherical crowns of the solder balls

Table Device and 176-ball BGA Package Maximum Weight
22 AT91M55800A

Soldering Profile

AT91M55800A

Table 12 gives the recommended soldering profile from J-STD-20.

Table Soldering Profile

Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range

Ramp-down Rate Time 25°C to Peak Temperature

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Datasheet ID: AT91M55800-33AI 519121