AT45DB642D-CU

AT45DB642D-CU Datasheet

AT45DB642D

Part	Datasheet
AT45DB642D-CU	AT45DB642D-CU (pdf)

Related Parts	Information
AT45DB642D-CNU	AT45DB642D-CNU
AT45DB642D-TU	AT45DB642D-TU

PDF Datasheet Preview
• Single 2.7V - 3.6V Supply • Dual-interface Architecture RapidS Serial Interface 66 MHz Maximum Clock Frequency SPI Compatible Modes 0 and 3 Rapid8 8-bit Interface 50 MHz Maximum Clock Frequency • User Configurable Page Size 1024 Bytes per Page 1056 Bytes per Page Size Can Be Factory Pre-configured for 1024 Bytes • Page Program Operation Intelligent Programming Operation 8192 Pages 1024/1056 Bytes/Page Main Memory • Flexible Erase Options Page Erase 1 Kbyte Block Erase 8 Kbytes Sector Erase 256 Kbytes Chip Erase 64 Mbits • Two SRAM Data Buffers 1024/1056 Bytes Allows Receiving of Data while Reprogramming the Flash Array • Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications • Low-power Dissipation 10 mA Active Read Current Typical Serial Interface 10 mA Active Read Current Typical 8-bit Interface 25 µA Standby Current Typical 15 µA Deep Power Down Typical • Hardware and Software Data Protection Features Individual Sector • Permanent Sector Lockdown for Secure Code and Data Storage Individual Sector • Security 128-byte Security Register 64-byte User Programmable Space Unique 64-byte Device Identifier • JEDEC Standard Manufacturer and Device ID Read • 100,000 Program/Erase Cycles Per Page Minimum • Data Retention 20 Years • Green Pb/Halide-free/RoHS Compliant Packaging Options • Temperature Range Industrial -40°C to +85°C 64-megabit 2.7-volt Dual-interface AT45DB642D The AT45DB642D is a 2.7-volt, dual-interface sequential access Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB642D supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial interface is SPI compatible for frequencies up to 66 MHz. The dual-interface allows a dedicated serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller or vice versa. However, the use of either interface is purely optional. Its 69,206,016 bits of memory are organized as 8,192 pages of 1,024 bytes binary page size or 1,056 bytes standard DataFlash page size each. In addition to the main memory, the AT45DB642D also contains two SRAM buffers of 1,024 binary buffer size bytes/1,056 bytes standard DataFlash buffer size each. The buffers allow receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM emulation bit or byte alterability is easily handled with a self-contained three step read-modifywrite operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses either a RapidS serial interface or a 8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential. To allow for simple in-system reprogrammability, the AT45DB642D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB642D is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK , or an 8-bit interface consisting of the input/output pins I/O7 I/O0 and the clock pin CLK . All programming and erase cycles are self-timed. 2 AT45DB642D AT45DB642D Pin Configurations and Pinouts Table Pin Configurations Symbol CS SCK/CLK SI SO I/O7 - I/O0 RESET RDY/BUSY Name and Function Chip Select Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode not Deep Power-Down mode , and the output pins SO or I/O7 - I/O0 will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pins SI or I/O7 - I/O0 . A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. Serial Clock This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI or I/O7 - I/O0 pins are always latched on the rising edge of SCK/CLK, while output data on the SO or I/O7 I/O0 pins are always clocked out on the falling edge of SCK/CLK. Serial Input The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. If the SER/BYTE pin is always driven low, the SI pin should be a “no connect”. Serial Output The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. If the SER/BYTE pin is always driven low, the SO pin should be a “no connect”. 8-bit Input/Output The I/O7-I/O0 pins are bidirectional and used to clock data into and out of the device. The I/O7-I/O0 pins are used for all data input, including opcodes and address sequences. The use of these pins is optional, and the pins should be treated as “no connect” if the SER/BYTE pin is not connected or if the SER/BYTE pin is always driven high externally. Write Protect When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register will be protected against program and erase operations regardless of whether the Enable Sector Protection command has been issued or not. The WP pin functions independently of the software controlled protection method. If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore the command and perform no operation. The device will return to the idle state once the CS pin has been deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be recognized by the device when the WP pin is asserted. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. Reset A low state on the reset pin RESET will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally. Ready/Busy This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state through an external pull-up resistor , will be pulled low during programming/erase operations, compare operations, and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed read and write operations to the other buffer can still be performed. Asserted State Type Input Input Input Output Input/ Output Input Input Output Table Symbol SER/BYTE Pin Configurations Continued “Power of 2” binary page size Configuration Register is a user-programmable nonvolatile register that allows the page size of the main memory to be configured for binary page size 1024 bytes or standard DataFlash page size 1056 bytes . The “power of 2” page size is a one-time programmable configuration register and once the device is configured for “power of 2” page size, it cannot be reconfigured again. The devices are initially shipped with the page size set to 1056 bytes. The user has the option of ordering binary page size 1024 bytes devices from the factory. For details, please refer to Section ”Ordering Information” on page For the binary “power of 2” page size to become effective, the following steps must be followed: Program the one-time programmable configuration resister using opcode sequence 3DH, 2AH, 80H and A6H please see Section Power cycle the device i.e. power down and power up again . User can now program the page for the binary page size. If the above steps are not followed in setting the page size prior to page programming, user may expect incorrect data during a read operation. Programming the Configuration Register To program the Configuration Register for “power of 2” binary page size, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Configuration Register should take place in a time of tP, during which time the Status Register will indicate that the device is busy. The device must be power-cycled after the completion of the program cycle to set the “power of 2” page size. If the device is powered-down before the completion of the program cycle, then setting the Configuration Register cannot be guaranteed. However, the user should check bit 0 of the status register to see whether the page size was configured for binary page size. If not, the command can be re-issued again. Command Power of Two Page Size Byte 1 3DH Byte 2 2AH Byte 3 80H Byte 4 A6H Figure Erase Sector Protection Register CS SI or IO7 - IO0 Opcode Byte 1 Each transition represents 8 bits Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 Manufacturer and Device ID Read Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information. To read the identification information, the CS pin must first be asserted and the opcode of 9FH must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00H indicating that no Extended Device Information follows. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional. Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Manufacturer and Device ID Information Hex Value 1FH Byte 1 Manufacturer ID JEDEC Assigned Code Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 Bit 0 1 Hex Value 28H Byte 2 Device ID Part 1 Family Code Density Code Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ordering Information Ordering Code Detail S SU Atmel Designator Product Family Device Density 64 = 64-megabit Interface 2 = Dual AT45DB642D Device Grade U = Matte Sn lead finish, industrial temperature range -40°C to +85°C Package Option CN = 8-lead, 6 x 8 mm CASON T = 28-lead, 8 x mm TSOP C = 24 Ball BGA Green Package Options Pb/Halide-free/RoHS Compliant Ordering Code 1 2 AT45DB642D-CNU AT45DB642D-CNU-SL954 3 AT45DB642D-CNU-SL955 4 AT45DB642D-TU Package 8CN3 28T Lead Finish Matte Sn Operating Voltage fSCK MHz 2.7V to 3.6V Operation Range Industrial -40°C to 85°C 2.7V to 3.6V AT45DB642D-CU 24C1 Matte Sn 2.7V to 3.6V Notes The shipping carrier option is not marked on the devices. Standard parts are shipped with the page size set to 1056 bytes. The user is able to configure these parts to a 1024-byte page size if desired. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 1024 bytes. Parts will have a 954 or SL954 marked on them. Parts ordered with suffix SL955 are shipped in tape and reel with the page size set to 1024 bytes. Parts will have a 954 or SL954 marked on them. 28T 8CN3 24C1 Package Type 28-lead, 8 x mm Plastic Thin Small Outline Package, Type I TSOP 8-pad 6 mm x 8 mm Chip Array Small Outline No Lead Package CASON 24-Ball, 6mm x 8mm x 1,4mm Ball Grid Array with a 1mm pitch 5 x 5 Ball Matrix 52 AT45DB642D Packaging Information 28T TSOP, Type 1 PIN 1 AT45DB642D 0º ~ 5º c Pin 1 Identifier Area D1 D SEATING PLANE GAGE PLANE This package conforms to JEDEC reference MO-183. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 D D1 E L L1 b c e MIN NOM MAX BASIC BASIC NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 28T, 28-lead 8 x mm Plastic Thin Small Outline Package, Type I TSOP 12/06/02 Added part number ordering code details for suffixes SL954/955. Added ordering code details. Changed tDIS Typ and Max to 27 ns and 35 ns, respectively, for RapidS interface. J March 2009 Changed Deep Power-Down Current values - Increased typical value from 9 µA to 15 µA. - Increased maximum value from 18 µA to 25 µA. K - April 2009 Updated Absolute Maximum Ratings Added 24C1 24 Ball BGA package Option Deleted DataFlash Card Package Option 56 AT45DB642D AT45DB642D Errata Chip Erase In a certain percentage of units, the Chip Erase feature may not function correctly and may adversely affect device operation. Therefore, it is recommended that the Chip Erase commands opcodes C7H, 94H, 80H, and 9AH not be used. Workaround Use Block Erase opcode 50H as an alternative. The Block Erase function is not affected by the Chip Erase issue. Resolution Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support Sales Contact Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2009 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, Everywhere You logo, logo and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

PDF Datasheet Preview

• Single 2.7V - 3.6V Supply
• Dual-interface Architecture

RapidS Serial Interface 66 MHz Maximum Clock Frequency SPI Compatible Modes 0 and 3

Rapid8 8-bit Interface 50 MHz Maximum Clock Frequency
• User Configurable Page Size
1024 Bytes per Page 1056 Bytes per Page Size Can Be Factory Pre-configured for 1024 Bytes
• Page Program Operation Intelligent Programming Operation 8192 Pages 1024/1056 Bytes/Page Main Memory
• Flexible Erase Options Page Erase 1 Kbyte Block Erase 8 Kbytes Sector Erase 256 Kbytes Chip Erase 64 Mbits
• Two SRAM Data Buffers 1024/1056 Bytes Allows Receiving of Data while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications
• Low-power Dissipation 10 mA Active Read Current Typical Serial Interface 10 mA Active Read Current Typical 8-bit Interface 25 µA Standby Current Typical 15 µA Deep Power Down Typical
• Hardware and Software Data Protection Features Individual Sector
• Permanent Sector Lockdown for Secure Code and Data Storage Individual Sector
• Security 128-byte Security Register 64-byte User Programmable Space Unique 64-byte Device Identifier
• JEDEC Standard Manufacturer and Device ID Read
• 100,000 Program/Erase Cycles Per Page Minimum
• Data Retention 20 Years
• Green Pb/Halide-free/RoHS Compliant Packaging Options
• Temperature Range Industrial -40°C to +85°C
64-megabit 2.7-volt Dual-interface

AT45DB642D

The AT45DB642D is a 2.7-volt, dual-interface sequential access Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB642D supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial interface is SPI compatible for frequencies up to 66 MHz. The dual-interface allows a dedicated serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller or vice versa. However, the use of either interface is purely optional. Its 69,206,016 bits of memory are organized as 8,192 pages of 1,024 bytes binary page size or 1,056 bytes standard DataFlash page size each. In addition to the main memory, the AT45DB642D also contains two SRAM buffers of 1,024 binary buffer size bytes/1,056 bytes standard DataFlash buffer size each. The buffers allow receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM emulation bit or byte alterability is easily handled with a self-contained three step read-modifywrite operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses either a RapidS serial interface or a 8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential.

To allow for simple in-system reprogrammability, the AT45DB642D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB642D is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK , or an 8-bit interface consisting of the input/output pins I/O7 I/O0 and the clock pin CLK .

All programming and erase cycles are self-timed.
2 AT45DB642D

AT45DB642D

Pin Configurations and Pinouts

Table Pin Configurations

Symbol CS SCK/CLK SI SO I/O7 - I/O0

RESET RDY/BUSY

Name and Function

Chip Select Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode not Deep Power-Down mode , and the output pins SO or I/O7 - I/O0 will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pins SI or I/O7 - I/O0 .

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.

Serial Clock This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI or I/O7 - I/O0 pins are always latched on the rising edge of SCK/CLK, while output data on the SO or I/O7 I/O0 pins are always clocked out on the falling edge of SCK/CLK.

Serial Input The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. If the SER/BYTE pin is always driven low, the SI pin should be a “no connect”.

Serial Output The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. If the SER/BYTE pin is always driven low, the SO pin should be a “no connect”.
8-bit Input/Output The I/O7-I/O0 pins are bidirectional and used to clock data into and out of the device. The I/O7-I/O0 pins are used for all data input, including opcodes and address sequences. The use of these pins is optional, and the pins should be treated as “no connect” if the SER/BYTE pin is not connected or if the SER/BYTE pin is always driven high externally.

Write Protect When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register will be protected against program and erase operations regardless of whether the Enable Sector Protection command has been issued or not. The WP pin functions independently of the software controlled protection method. If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore the command and perform no operation. The device will return to the idle state once the CS pin has been deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be recognized by the device when the WP pin is asserted.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible.

Reset A low state on the reset pin RESET will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally.

Ready/Busy This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state through an external pull-up resistor , will be pulled low during programming/erase operations, compare operations, and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed read and write operations to the other buffer can still be performed.

Asserted

State

Type

Input

Input

Input

Output

Input/ Output

Input

Input

Output

Table Symbol

SER/BYTE

Pin Configurations Continued
“Power of 2” binary page size Configuration Register is a user-programmable nonvolatile register that allows the page size of the main memory to be configured for binary page size 1024 bytes or standard DataFlash page size 1056 bytes . The “power of 2” page size is a one-time programmable configuration register and once the device is configured for “power of 2” page size, it cannot be reconfigured again. The devices are initially shipped with the page size set to 1056 bytes. The user has the option of ordering binary page size 1024 bytes devices from the factory. For details, please refer to Section ”Ordering Information” on page

For the binary “power of 2” page size to become effective, the following steps must be followed:

Program the one-time programmable configuration resister using opcode sequence 3DH, 2AH, 80H and A6H please see Section

Power cycle the device i.e. power down and power up again . User can now program the page for the binary page size. If the above steps are not followed in setting the page size prior to page programming, user may expect incorrect data during a read operation.

Programming the Configuration Register

To program the Configuration Register for “power of 2” binary page size, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Configuration Register should take place in a time of tP, during which time the Status Register will indicate that the device is busy. The device must be power-cycled after the completion of the program cycle to set the “power of 2” page size. If the device is powered-down before the completion of the program cycle, then setting the Configuration Register cannot be guaranteed. However, the user should check bit 0 of the status register to see whether the page size was configured for binary page size. If not, the command can be re-issued again.

Command Power of Two Page Size

Byte 1 3DH

Byte 2 2AH

Byte 3 80H

Byte 4 A6H

Figure Erase Sector Protection Register CS

SI or IO7 - IO0

Opcode Byte 1

Each transition represents 8 bits

Opcode Byte 2

Opcode Byte 3

Opcode Byte 4

Manufacturer and Device ID Read

Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the
device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information.

To read the identification information, the CS pin must first be asserted and the opcode of 9FH must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00H indicating that no Extended Device Information follows. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional.

Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Manufacturer and Device ID Information

Hex Value 1FH

Byte 1 Manufacturer ID

JEDEC Assigned Code

Bit 7 0

Bit 6 0

Bit 5 0

Bit 4 1

Bit 3 1

Bit 2 1

Bit 1

Bit 0 1

Hex Value 28H

Byte 2 Device ID Part 1

Family Code

Density Code

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0
Ordering Information
Ordering Code Detail S SU

Atmel Designator

Product Family

Device Density
64 = 64-megabit

Interface
2 = Dual

AT45DB642D

Device Grade

U = Matte Sn lead finish, industrial temperature range -40°C to +85°C

Package Option

CN = 8-lead, 6 x 8 mm CASON T = 28-lead, 8 x mm TSOP C = 24 Ball BGA

Green Package Options Pb/Halide-free/RoHS Compliant
Ordering Code 1 2

AT45DB642D-CNU AT45DB642D-CNU-SL954 3 AT45DB642D-CNU-SL955 4

AT45DB642D-TU

Package 8CN3 28T

Lead Finish Matte Sn

Operating Voltage fSCK MHz
2.7V to 3.6V

Operation Range

Industrial -40°C to 85°C
2.7V to 3.6V

AT45DB642D-CU
24C1

Matte Sn
2.7V to 3.6V

Notes The shipping carrier option is not marked on the devices.

Standard parts are shipped with the page size set to 1056 bytes. The user is able to configure these parts to a 1024-byte page size if desired.

Parts ordered with suffix SL954 are shipped in bulk with the page size set to 1024 bytes. Parts will have a 954 or SL954 marked on them.

Parts ordered with suffix SL955 are shipped in tape and reel with the page size set to 1024 bytes. Parts will have a 954 or SL954 marked on them.
28T 8CN3 24C1

Package Type 28-lead, 8 x mm Plastic Thin Small Outline Package, Type I TSOP 8-pad 6 mm x 8 mm Chip Array Small Outline No Lead Package CASON 24-Ball, 6mm x 8mm x 1,4mm Ball Grid Array with a 1mm pitch 5 x 5 Ball Matrix
52 AT45DB642D

Packaging Information
28T TSOP, Type 1

PIN 1

AT45DB642D
0º ~ 5º c

Pin 1 Identifier Area D1 D

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-183. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

BASIC

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
28T, 28-lead 8 x mm Plastic Thin Small Outline Package, Type I TSOP
12/06/02
Added part number ordering code details for suffixes SL954/955. Added ordering code details.

Changed tDIS Typ and Max to 27 ns and 35 ns, respectively, for RapidS interface.

J March 2009

Changed Deep Power-Down Current values - Increased typical value from 9 µA to 15 µA. - Increased maximum value from 18 µA to 25 µA.

K - April 2009

Updated Absolute Maximum Ratings Added 24C1 24 Ball BGA package Option Deleted DataFlash Card Package Option
56 AT45DB642D

AT45DB642D

Errata

Chip Erase

In a certain percentage of units, the Chip Erase feature may not function correctly and may adversely affect device operation. Therefore, it is recommended that the Chip Erase commands opcodes C7H, 94H, 80H, and 9AH not be used.

Workaround Use Block Erase opcode 50H as an alternative. The Block Erase function is not affected by the Chip Erase issue.

Resolution

Headquarters

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600

International

Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369

Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Product Contact

Web Site

Literature Requests

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More datasheets: 3582 | 17000541A | 208577150001025 | 208577128002025 | 208577048002025 | 168577048001025 | 168577096001025 | 208577096002025 | 108577096002025 | 108577048001025

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Datasheet ID: AT45DB642D-CU 519053