AT45DB321D-CU

AT45DB321D-CU Datasheet

Atmel AT45DB321D

Part	Datasheet
AT45DB321D-CU	AT45DB321D-CU (pdf)

Related Parts	Information
AT45DB321D-SU-2.5	AT45DB321D-SU-2.5
AT45DB321D-SU	AT45DB321D-SU
AT45DB321D-MWU	AT45DB321D-MWU
AT45DB321D-MU	AT45DB321D-MU
AT45DB321D-TU	AT45DB321D-TU

PDF Datasheet Preview
Atmel AT45DB321D 32Mb, 2.5V or 2.7V Atmel DataFlash DATASHEET ● Single 2.5V - 3.6V or 2.7V - 3.6V supply ● RapidS serial interface 66MHz maximum clock frequency ● SPI compatible modes 0 and 3 ● User configurable page size ● 512 bytes per page ● 528 bytes per page ● Page size can be factory preconfigured for 512 bytes ● Page program operation ● Intelligent programming operation ● 8,192 pages 512/528 bytes/page main memory ● Flexible erase options ● Page erase 512 bytes ● Block erase 4KB ● Sector erase 64KB ● Chip erase 32Mb ● Two SRAM data buffers 512/528 bytes ● Allows receiving data while reprogramming the flash array ● Continuous read capability through entire array ● Ideal for code shadowing applications ● Low power dissipation ● 7mA active read current ,typical ● 25µA standby current, typical ● 15uA deep power down, typical ● Hardware and software data protection features ● Individual sector ● Sector lockdown for secure code and data storage ● Individual sector ● Security 128-byte security register ● 64-byte user programmable space ● Unique 64-byte device identifier ● JEDEC standard manufacturer and device ID read ● 100,000 program/erase cycles per page, minimum ● Data retention 20 years ● Industrial temperature range ● Green Pb/halide-free/RoHS compliant packaging options The Atmel AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of digital voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the Atmel RapidS serial interface for applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz. The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data while a page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM electrically erasable and programmable read-only memory emulation bit or byte alterability is easily handled with a selfcontained, three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with multiple address lines and a parallel interface, Atmel devices use a RapidS serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage and low power are essential. To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the serial input SI , serial output SO , and serial clock SCK lines. All programming and erase cycles are self timed. Figure Pin configurations and pinouts. MLF 1 VDFN Top View SI 1 SCK 2 RESET 3 8 SO 7 GND 6 VCC 5 WP Note: The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND. BGA Package Ball-out Top View 12 3 4 5 B NC SCK GND VCC NC NC CS RDY/BSY WP NC NC SO SI RESET NC RDY/BUSY RESET WP NC VCC GND NC CS SCK SI SO SI SCK RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SOIC Top View 7 GND 6 VCC TSOP Type 1 Top View 28 NC 27 NC 26 NC 25 NC 24 NC 23 NC 22 NC 21 NC 20 NC 19 NC 18 NC 17 NC 16 NC 15 NC Note: TSOP package is not recommended for new designs. Future die shrinks will support 8-pin packages only. Atmel AT45DB321D Table Pin Configurations Symbol CS SCK SI SO WP RESET RDY/BUSY VCC GND Name and Function Chip Select Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode not deep powerdown mode , and the output pin SO will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin SI . A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. Serial Clock This pin is used to provide a clock to the device, and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin are always latched on the rising edge of SCK, while output data on the SO pin are always clocked out on the falling edge of SCK. “Power of two” binary page size configuration register is a user programmable, nonvolatile register that allows the page size of the main memory to be configured for binary page size 512 bytes or standard DataFlash page size 528 bytes . The power of two page size is a one-time programmable configuration register, and once the device is configured for power of two page size, it cannot be reconfigured again. The devices are initially shipped with the page size set to 528 bytes. The user has the option of ordering binary page size 512-byte devices from the factory. For details, please refer to Section “Ordering Information” on page For the binary power of two page size to become effective, the following steps must be followed Program the one-time programmable configuration resister using the opcode sequence 3DH, 2AH, 80H, and A6H see Section Power cycle the device i.e., power down and power up again . The page for the binary page size can now be programmed. If the above steps to set the page size prior to page programming are not followed, incorrect data during a read operation may be encountered. Programming the Configuration Register To program the configuration register for power of two binary page size, the CS pin must first be asserted, as it would be with any other command. Once the CS pin has been asserted, the appropriate four-byte opcode sequence must be clocked into the device in the correct order. The four-byte opcode sequence must start with 3DH, followed by 2AH, 80H, and A6H. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the configuration register should take place in a maximum time of tP, during which time the status register will indicate that the device is busy. The device must be power cycled after the completion of the program cycle to set the power of two page size. If the device is powered-down before the completion of the program cycle, then setting the configuration register cannot be guaranteed. However, the user should check bit 0 of the status register to see whether the page size was configured for binary page size or not. If not, the command can be issued again. Table Programming the Configuration Register Command Power of two page size Byte 1 3DH Byte 2 2AH Byte 3 80H Byte 4 A6H Figure Erase Sector Protection Register Opcode byte 1 Each transition represents 8 bits Opcode byte 2 Opcode byte 3 Opcode byte 4 Manufacturer and Device ID Read Identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices.” The type of information that can be read from the device includes the JEDEC-defined manufacturer ID, the vendor-specific device ID, and the vendor-specific extended device information. To read the identification information, the CS pin must first be asserted, and then the opcode of 9FH must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte to be output will be the manufacturer ID, followed by two bytes of device ID information. The fourth byte output will be the extended device information string length, which will be 00H to indicate that no extended Atmel AT45DB321D 21 device information follows. As indicated in the JEDEC standard, reading the extended device information string length and any subsequent data is optional. Deasserting the CS pin will terminate the manufacturer and device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time, and does not require that a full byte of data be read. Manufacturer and Device ID Information Byte 1 Manufacturer ID Hex Value Bit 7 0 Bit 6 0 JEDEC Assigned Code Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 Manufacturer ID 1FH = Atmel Byte 2 Device ID Part 1 Hex Value Family Code Bit 7 Bit 6 Bit 5 Bit 4 0 Density Code Bit 3 Bit 2 Bit 1 Bit 0 1 Ordering Information Ordering Code Detail A T 4 5 D B 3 2 1 D MWU Atmel Designator Product Family Device Density 32 = 32-megabit Interface 1 = Serial Device Grade U = Matte Sn lead finish, industrial temperature range -40°C to +85°C Package Option M = 8-pad, 6 x 5 x 1mm MLF VDFN MW = 8-pad, 8 x 6 x 1mm MLF VDFN S = 8-lead, wide SOIC T = 28-lead, TSOP C = 24 Ball BGA Green Package Options Pb/Halide-free/RoHS Compliant Ordering Code 1 2 Package Lead Finish Operating Voltage AT45DB321D-MU AT45DB321D-MU-SL954 3 AT45DB321D-MU-SL955 4 8M1-A AT45DB321D-MWU AT45DB321D-MWU-SL954 3 AT45DB321D-MWU-SL955 4 Matte Sn 2.7V to 3.6V AT45DB321D-SU AT45DB321D-SU-SL954 3 AT45DB321D-SU-SL955 4 AT45DB321D-TU AT45DB321D-CU 24C3 Matte Sn 2.7V to 3.6V AT45DB321D-MU-2.5 AT45DB321D-SU-2.5 8M1-A 8S2 Matte Sn 2.5V to 3.6V fSCK MHz Operation Range 66 Industrial -40C to 85C 2.7V to 3.6V 66 50 Notes The shipping carrier option is not marked on the devices. Standard parts are shipped with the page size set to 528 bytes. The user is able to configure these parts to a 512-byte page size, if desired. Parts ordered with suffix SL954 are shipped in bulk, with the page size set to 512 bytes. Parts will have “954” or “SL954” marked on them. Parts ordered with suffix SL955 are shipped in tape and reel, with the page size set to 512 bytes. Parts will have “955” or “SL955” marked on them. 8M1-A 8MW 8S2 28T 24C3 Package Type 8-pad, 6 x 5 x 1.0mm, very thin micro lead-frame package MLF VDFN 8-pad, 8 x 6 x 1.0mm, very thin micro lead-frame package MLF VDFN 8-lead, 0.209in-wide, plastic gull wing small outline package EIAJ SOIC 28-lead, 8mm x 13.4mm, plastic thin small outline package, type I TSOP 24-ball, 6mm x 8mm x 1.4mm ball grid array with a 1mm pitch 5 x 5 ball matrix Atmel AT45DB321D 43 Packaging Information 8M1-A MLF VDFN Pin 1 ID 0 SIDE VIEW TOP VIEW A2 Pin #1 Notch BOTTOM VIEW A3 A1 COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Added the 2.5V VCC option Removed AT45DB321D-MWU-2.5 and AT45DB321D-TU-2.5 from the ordering Information table Updated Absolute Maximum Ratings Added 24C1 24 Ball BGA package Option Deleted Atmel DataFlash Card Package Option Changed deep power-down current values - Increased typical value from 5µA to 15µA - Increased maximum value from 15µA to 25µA Changed tDIS Typ and Max to 27ns and 35ns, respectively Corrected typographical errors in Sector Erase section. Corrected A17+A16 from x Don’t care to A for opcode 7Ch in Table 15-6 Corrected PA8+PA7 from x Don’t care to P for opcode 7Ch in Table 15-7 Added part number ordering code details for suffixes SL954/955 Added ordering code details Added additional text to “power of two” binary page size option Changed tVSCL from 50µs to 70µs Changed tRDPD from 30µs to 35µs Changed tXFR and tCOMP values from 400µs to 200µs Removed AT45DB321D-CNU from ordering information and corresponding 8CN3 package Added AT45DB321D-CNU to ordering information and corresponding 8CN3 package Removed “not recommended for new designs” comment from 8MW package drawing Removed “not recommended for new designs” note from ordering information for 8MW package Added errata regarding Chip Erase Added AT45DB321D-SU to ordering information and corresponding 8S2 package Corrected typographical errors Added 8 x 6mm MLF VDFN package Changed the sector size of 0a and 0b to 8 pages and 120 pages respectively Changed the Product Version Code to 00001 Added preliminary Changed the sector size from 256-Kbytes to 64-Kbytes Added the “Legacy Commands” table Atmel AT45DB321D 49 3597A Date 01/2006 11/2005 Comments Added 6 x 5mm MLF VDFN package Added text, in “Programming the Configuration Register”, to indicate that power cycling is required to switch to “power of two” page size after the opcode enable has been executed. Corrected typographical error regarding the opcode for chip erase in “Program and Erase Commands” table Initial release Errata Chip Erase Issue In a certain percentage of units, the chip erase feature may not function correctly and may adversely affect device operation. Therefore, it is recommended that the chip erase commands opcodes C7H, 94H, 80H, and 9AH not be used. Workaround Use block erase opcode 50H as an alternative. The block erase function is not affected by the chip erase issue. Atmel AT45DB321D 50 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel +1 408 441-0311 Fax +1 408 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Roa Kwun Tong, Kowloon HONG KONG Tel +852 2245-6100 Fax +852 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel +49 89-31970-0 Fax +49 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel +81 3 3523-3551 Fax +81 3 3523-7581 Atmel logo and combinations thereof, RapidS , and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

PDF Datasheet Preview

Atmel AT45DB321D
32Mb, 2.5V or 2.7V Atmel DataFlash

DATASHEET
● Single 2.5V - 3.6V or 2.7V - 3.6V supply ● RapidS serial interface 66MHz maximum clock frequency
● SPI compatible modes 0 and 3 ● User configurable page size
● 512 bytes per page ● 528 bytes per page ● Page size can be factory preconfigured for 512 bytes ● Page program operation ● Intelligent programming operation ● 8,192 pages 512/528 bytes/page main memory ● Flexible erase options ● Page erase 512 bytes ● Block erase 4KB ● Sector erase 64KB ● Chip erase 32Mb ● Two SRAM data buffers 512/528 bytes ● Allows receiving data while reprogramming the flash array ● Continuous read capability through entire array ● Ideal for code shadowing applications ● Low power dissipation ● 7mA active read current ,typical ● 25µA standby current, typical ● 15uA deep power down, typical ● Hardware and software data protection features ● Individual sector ● Sector lockdown for secure code and data storage ● Individual sector ● Security 128-byte security register ● 64-byte user programmable space ● Unique 64-byte device identifier ● JEDEC standard manufacturer and device ID read ● 100,000 program/erase cycles per page, minimum ● Data retention 20 years ● Industrial temperature range ● Green Pb/halide-free/RoHS compliant packaging options

The Atmel AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of digital voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the Atmel RapidS serial interface for applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz. The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data while a page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM electrically erasable and programmable read-only memory emulation bit or byte alterability is easily handled with a selfcontained, three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with multiple address lines and a parallel interface, Atmel devices use a RapidS serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage and low power are essential.

To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the serial input SI , serial output SO , and serial clock SCK lines.

All programming and erase cycles are self timed.

Figure Pin configurations and pinouts.

MLF 1 VDFN Top View

SI 1 SCK 2 RESET 3
8 SO 7 GND 6 VCC 5 WP

Note:

The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND.

BGA Package Ball-out Top View
12 3 4 5

B NC SCK GND VCC NC

NC CS RDY/BSY WP NC

NC SO

SI RESET NC

RDY/BUSY RESET WP NC VCC GND NC CS SCK SI SO

SI SCK RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14

SOIC Top View
7 GND
6 VCC

TSOP Type 1 Top View
28 NC 27 NC 26 NC 25 NC 24 NC 23 NC 22 NC 21 NC 20 NC 19 NC 18 NC 17 NC 16 NC 15 NC

Note:

TSOP package is not recommended for new designs. Future die shrinks will support 8-pin packages only.

Atmel AT45DB321D

Table Pin Configurations

Symbol CS

SCK SI SO WP

RESET

RDY/BUSY VCC GND

Name and Function

Chip Select Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode not deep powerdown mode , and the output pin SO will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin SI .

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.

Serial Clock This pin is used to provide a clock to the device, and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin are always latched on the rising edge of SCK, while output data on the SO pin are always clocked out on the falling edge of SCK.
“Power of two” binary page size configuration register is a user programmable, nonvolatile register that allows the page size of the main memory to be configured for binary page size 512 bytes or standard DataFlash page size 528 bytes . The power of two page size is a one-time programmable configuration register, and once the device is configured for power of two page size, it cannot be reconfigured again. The devices are initially shipped with the page size set to 528 bytes. The user has the option of ordering binary page size 512-byte devices from the factory. For details, please refer to Section “Ordering Information” on page

For the binary power of two page size to become effective, the following steps must be followed Program the one-time programmable configuration resister using the opcode sequence 3DH, 2AH, 80H, and A6H see Section Power cycle the device i.e., power down and power up again . The page for the binary page size can now be programmed.

If the above steps to set the page size prior to page programming are not followed, incorrect data during a read operation may be encountered.

Programming the Configuration Register

To program the configuration register for power of two binary page size, the CS pin must first be asserted, as it would be with any other command. Once the CS pin has been asserted, the appropriate four-byte opcode sequence must be clocked into the device in the correct order. The four-byte opcode sequence must start with 3DH, followed by 2AH, 80H, and A6H. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the configuration register should take place in a maximum time of tP, during which time the status register will indicate that the device is busy. The device must be power cycled after the completion of the program cycle to set the power of two page size. If the device is powered-down before the completion of the program cycle, then setting the configuration register cannot be guaranteed. However, the user should check bit 0 of the status register to see whether the page size was configured for binary page size or not. If not, the command can be issued again.

Table Programming the Configuration Register

Command Power of two page size

Byte 1 3DH

Byte 2 2AH

Byte 3 80H

Byte 4 A6H

Figure Erase Sector Protection Register

Opcode byte 1

Each transition represents 8 bits

Opcode byte 2

Opcode byte 3

Opcode byte 4

Manufacturer and Device ID Read

Identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices.” The type of information that can be read from the device includes the JEDEC-defined manufacturer ID, the vendor-specific device ID, and the vendor-specific extended device information.

To read the identification information, the CS pin must first be asserted, and then the opcode of 9FH must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte to be output will be the manufacturer ID, followed by two bytes of device ID information. The fourth byte output will be the extended device information string length, which will be 00H to indicate that no extended

Atmel AT45DB321D 21
device information follows. As indicated in the JEDEC standard, reading the extended device information string length and any subsequent data is optional.

Deasserting the CS pin will terminate the manufacturer and device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time, and does not require that a full byte of data be read.

Manufacturer and Device ID Information

Byte 1 Manufacturer ID

Hex Value

Bit 7 0

Bit 6 0

JEDEC Assigned Code

Bit 5 Bit 4 Bit 3 Bit 2

Bit 1

Bit 0 1

Manufacturer ID 1FH = Atmel

Byte 2 Device ID Part 1

Hex Value

Family Code

Bit 7 Bit 6 Bit 5

Bit 4 0

Density Code

Bit 3 Bit 2 Bit 1

Bit 0 1
Ordering Information
Ordering Code Detail

A T 4 5 D B 3 2 1 D MWU

Atmel Designator

Product Family

Device Density
32 = 32-megabit

Interface
1 = Serial

Device Grade

U = Matte Sn lead finish, industrial temperature range -40°C to +85°C

Package Option

M = 8-pad, 6 x 5 x 1mm MLF VDFN MW = 8-pad, 8 x 6 x 1mm MLF VDFN S = 8-lead, wide SOIC T = 28-lead, TSOP C = 24 Ball BGA

Green Package Options Pb/Halide-free/RoHS Compliant
Ordering Code 1 2

Package Lead Finish

Operating Voltage

AT45DB321D-MU AT45DB321D-MU-SL954 3 AT45DB321D-MU-SL955 4
8M1-A

AT45DB321D-MWU AT45DB321D-MWU-SL954 3 AT45DB321D-MWU-SL955 4

Matte Sn
2.7V to 3.6V

AT45DB321D-SU

AT45DB321D-SU-SL954 3

AT45DB321D-SU-SL955 4

AT45DB321D-TU

AT45DB321D-CU
24C3

Matte Sn
2.7V to 3.6V

AT45DB321D-MU-2.5 AT45DB321D-SU-2.5
8M1-A 8S2

Matte Sn
2.5V to 3.6V
fSCK MHz Operation Range
66 Industrial
-40C to 85C 2.7V to 3.6V
66 50

Notes The shipping carrier option is not marked on the devices.

Standard parts are shipped with the page size set to 528 bytes. The user is able to configure these parts to a 512-byte page size, if desired.

Parts ordered with suffix SL954 are shipped in bulk, with the page size set to 512 bytes. Parts will have “954” or “SL954” marked on them.

Parts ordered with suffix SL955 are shipped in tape and reel, with the page size set to 512 bytes. Parts will have “955” or “SL955” marked on them.
8M1-A 8MW 8S2 28T 24C3

Package Type 8-pad, 6 x 5 x 1.0mm, very thin micro lead-frame package MLF VDFN 8-pad, 8 x 6 x 1.0mm, very thin micro lead-frame package MLF VDFN 8-lead, 0.209in-wide, plastic gull wing small outline package EIAJ SOIC 28-lead, 8mm x 13.4mm, plastic thin small outline package, type I TSOP 24-ball, 6mm x 8mm x 1.4mm ball grid array with a 1mm pitch 5 x 5 ball matrix

Atmel AT45DB321D 43

Packaging Information
8M1-A MLF VDFN

Pin 1 ID
0 SIDE VIEW

TOP VIEW A2

Pin #1 Notch

BOTTOM VIEW

A3 A1

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE
Added the 2.5V VCC option Removed AT45DB321D-MWU-2.5 and AT45DB321D-TU-2.5 from the ordering Information table

Updated Absolute Maximum Ratings Added 24C1 24 Ball BGA package Option Deleted Atmel DataFlash Card Package Option

Changed deep power-down current values - Increased typical value from 5µA to 15µA - Increased maximum value from 15µA to 25µA

Changed tDIS Typ and Max to 27ns and 35ns, respectively

Corrected typographical errors in Sector Erase section. Corrected A17+A16 from x Don’t care to A for opcode 7Ch in Table 15-6 Corrected PA8+PA7 from x Don’t care to P for opcode 7Ch in Table 15-7
Added part number ordering code details for suffixes SL954/955 Added ordering code details
Added additional text to “power of two” binary page size option Changed tVSCL from 50µs to 70µs Changed tRDPD from 30µs to 35µs Changed tXFR and tCOMP values from 400µs to 200µs Removed AT45DB321D-CNU from ordering information and corresponding 8CN3 package
Added AT45DB321D-CNU to ordering information and corresponding 8CN3 package Removed “not recommended for new designs” comment from 8MW package drawing
Removed “not recommended for new designs” note from ordering information for 8MW package
Added errata regarding Chip Erase Added AT45DB321D-SU to ordering information and corresponding 8S2 package

Corrected typographical errors

Added 8 x 6mm MLF VDFN package Changed the sector size of 0a and 0b to 8 pages and 120 pages respectively Changed the Product Version Code to 00001

Added preliminary Changed the sector size from 256-Kbytes to 64-Kbytes Added the “Legacy Commands” table

Atmel AT45DB321D 49
3597A

Date 01/2006
11/2005

Comments

Added 6 x 5mm MLF VDFN package Added text, in “Programming the Configuration Register”, to indicate that power cycling is
required to switch to “power of two” page size after the opcode enable has been executed. Corrected typographical error regarding the opcode for chip erase in “Program and Erase

Commands” table

Initial release

Errata

Chip Erase

Issue In a certain percentage of units, the chip erase feature may not function correctly and may adversely affect device operation. Therefore, it is recommended that the chip erase commands opcodes C7H, 94H, 80H, and 9AH not be used.

Workaround Use block erase opcode 50H as an alternative. The block erase function is not affected by the chip erase issue.

Atmel AT45DB321D 50

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel +1 408 441-0311 Fax +1 408 487-2600

Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Roa Kwun Tong, Kowloon HONG KONG Tel +852 2245-6100 Fax +852 2722-1369

Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel +49 89-31970-0 Fax +49 89-3194621

Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel +81 3 3523-3551 Fax +81 3 3523-7581

Atmel logo and combinations thereof, RapidS , and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT45DB321D-CU Datasheet file may be downloaded here without warranties.

Datasheet ID: AT45DB321D-CU 519051