AT45DB161E-MHD2B-T

AT45DB161E-MHD2B-T Datasheet

Atmel AT45DB161E

Part	Datasheet
AT45DB161E-MHD2B-T	AT45DB161E-MHD2B-T (pdf)

Related Parts	Information
AT45DB161E-SHD-T	AT45DB161E-SHD-T
AT45DB161E-SSHD2B-T	AT45DB161E-SSHD2B-T
AT45DB161E-SSHD-B	AT45DB161E-SSHD-B
AT45DB161E-MHD-T	AT45DB161E-MHD-T
AT45DB161E-SSHD-T	AT45DB161E-SSHD-T
AT45DB161E-MHD-Y	AT45DB161E-MHD-Y
AT45DB161E-SHD-B	AT45DB161E-SHD-B
AT45DB161E-CCUD-T	AT45DB161E-CCUD-T
AT45DB161E-SHD2B-T	AT45DB161E-SHD2B-T

PDF Datasheet Preview
Atmel AT45DB161E 16-Mbits DataFlash with Extra 512-Kbits , 2.3V or 2.5V Minimum SPI Serial Flash Memory PRELIMINARY DATASHEET Single 2.3V - 3.6V or 2.5V - 3.6V supply Serial Peripheral Interface SPI compatible Supports SPI modes 0 and 3 Supports RapidS operation Continuous Read capability through entire array Up to 85MHz Low-power Read option up to 10MHz Clock-to-output time tV of 6ns maximum User configurable page size 512 bytes per page 528 bytes per page default Page size can be factory pre-configured for 512 bytes Two fully independent SRAM data buffers 512/528 bytes Allows receiving data while reprogramming the Main Memory Array Flexible programming options Byte/Page program 1 to 512/528 bytes directly into main memory Buffer Write Buffer to Main Memory Page Program Flexible Erase options Page Erase 512/528 bytes Block Erase 4KB Sector Erase 128KB Chip Erase 16-Mbits Program and Erase Suspend/Resume Advanced hardware and software data protection features Individual sector protection Individual sector lockdown to make any sector permanently read-only 128-byte, One-Time Programmable OTP Security Register 64 bytes factory programmed with a unique identifier 64 bytes user programmable Software controlled reset JEDEC Standard Manufacturer and Device ID Read Low-power dissipation 500nA Ultra-Deep Power-Down current typical 3uA Deep Power-Down current typical 25uA Standby current typical 11mA Active Read current typical Endurance 100,000 program/erase cycles per page minimum Data retention 20 years Complies with full industrial temperature range Green Pb/Halide-free/RoHS compliant packaging options 8-lead SOIC wide 8-pad Ultra-thin DFN 5 x 6 x 0.6mm 9-ball Chip-scale BGA 5 x 5 x 1.2mm The Atmel AT45DB161E is a 2.3V or 2.5V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB161E also supports RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organized as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB161E also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a system's ability to write a continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pademory, and E2PROM emulation bit or byte alterability can be easily handled with a self-contained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the Atmel uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage, and low-power are essential. To allow for simple in-system re-programmability, the AT45DB161E does not require high input voltages for programming. The device operates from a single 2.3V to 3.6V or 2.5V to 3.6V power supply for the erase and program and read operations. The AT45DB161E is enabled through the Chip Select pin CS and accessed via a 3-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK . All programming and erase cycles are self-timed. Pin Configurations and Pinouts Figure Pinouts 8-lead SOIC Top View SI 1 SCK 2 RESET 3 8 SO 7 GND 6 VCC 5 WP 8-pad UDFN Top View SI 1 SCK 2 RESET 3 8 SO 7 GND 6 VCC 5 WP 8-ball CBGA Top View SCK GND VCC CS NC WP SI RST Note The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential. This pad can be a “no connect” or connected to GND. Atmel AT45DB161E [PRELIMINARY DATASHEET] Table Pin Configurations Symbol CS SCK SI SO RESET VCC GND Name and Function Devices are initially shipped from Atmel with the buffer and page sizes set to 528 bytes. Devices can be ordered from Atmel pre-configured for the "power of 2" binary size of 512 bytes. For details, see Section Ordering Information on page To configure the device for "power of 2" binary page size 512 bytes , a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and A6h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed configuration process and nonvolatile register program cycle. The programming of the nonvolatile register should take place in a time of tEP, during which time the RDY/BUSY bit in the Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 512 bytes. To configure the device for standard DataFlash page size 528 bytes , a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and A7h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initial the internally self-timed configuration process and nonvolatile register program cycle. The programming of the nonvolatile register should take place in a time of tEP, during which time the RDY/BUSY bit in the Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 528 bytes. Table Buffer and Page Size Configuration Commands Command "Power of 2" binary page size 512 bytes DataFlash page size 528 bytes Byte 1 3Dh Byte 2 2Ah Byte 3 80h Byte 4 A6h A7h Figure Buffer and Page Size Configuration CS SI Each transition represents eight bits Opcode Byte 4 Atmel AT45DB161E [PRELIMINARY DATASHEET] 35 Manufacturer and Device ID Read Identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. The identification method and the command opcode comply with the JEDEC Standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC-defined Manufacturer ID, the vendor-specific Device ID, and the vendor-specific Extended Device Information. The Read Manufacturer and Device ID command is limited to a maximum clock frequency of fCLK. Since not all Flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the application can be identified properly. Once the identification process is complete, the application can then increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies. To read the identification information, the CS pin must first be asserted and then the opcode 9Fh must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO during the subsequent clock cycles. The first byte to be output will be the Manufacturer ID, followed by two bytes of the Device ID information. The fourth byte output will be the Extended Device Information EDI String Length, which will be 01h indicating that one byte of EDI data follows. After the one byte of EDI data is output, the SO pin will go into a high-impedance state therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC Standard, reading the EDI String Length and any subsequent data is optional. Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table Manufacturer and Device ID Information Byte No. Data Type Manufacturer ID Device ID Byte 1 Device ID Byte 2 [Optional to Read] Extended Device Information EDI String Length [Optional to Read] EDI Byte 1 Value 1Fh 26h 00h 01h 00h Table Manufacturer and Device ID Details Data Type Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details Manufacturer ID JEDEC Assigned Code 1Fh JEDEC code 0001 1111 1Fh for Atmel Device ID Byte 1 Family Code Density Code Family code 001 AT45Dxxx Family Density code 00110 16-Mbit Device ID Byte 2 Sub Code Product Variant Ordering Information Ordering Detail Atmel Designator AT 4 5 D B 1 6 1 E - S F U - B Product Family 45DB = Atmel DataFlash Device Density 16 = 16-Mbit Interface 1 = Serial Shipping Carrier Option B = Bulk tubes T = Tape and reel Y = Trays Device Grade H = Green, NiPdAu lead finish, Industrial temperature range to +85°C U = Green, Matte Sn or Sn alloy, Industrial temperature range to +85°C Operating Voltage D = 2.5V minimum 2.5V to 3.6V F = 2.3V minimum 2.3V to 3.6V Package Option SS= 8-lead, wide SOIC S = 8-lead, wide SOIC M = 8-pad, 5 x 6 x 0.6mm UDFN CC= 9-ball, 3 x 3 1mm pitch CBGA Atmel AT45DB161E [PRELIMINARY DATASHEET] 62 Ordering Codes Atmel Ordering Code AT45DB161E-SSHD-B 1 AT45DB161E-SSHD-T 1 AT45DB161E-SHD-B 1 2 AT45DB161E-SHD-T 1 2 AT45DB161E-MHD-Y 1 AT45DB161E-MHD-T 1 AT45DB161E-CCUD-T Package Lead Finish Operating Voltage fSCK 8S2 8MA1 9C1 NiPdAu SnAgCu 2.5V to 3.6V 85MHz AT45DB161E-SSHF-B 1 AT45DB161E-SSHF-T 1 AT45DB161E-SHF-B 1 2 AT45DB161E-SHF-T 1 2 AT45DB161E-MHF-Y 1 AT45DB161E-MHF-T 1 8S1 8S2 8MA1 NiPdAu 2.3V to 3.6V Notes The shipping carrier suffix is not marked on the device. Not recommended for new design. Use the 8S1 package option. 85MHz Device Grade Industrial -40C to 85C Industrial -40C to 85C 8S1 8S2 8MA1 9C1 Package Type 8-lead wide, Plastic Gull Wing Small Outline JEDEC SOIC 8-lead wide, Plastic Gull Wing Small Outline EIAJ SOIC 8-pad 5 x 6 x 0.6mm body , Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead UDFN 9-ball 3 x 3 array x 1mm pitch, Chip-scale Ball Grid Array CBGA Atmel AT45DB161E [PRELIMINARY DATASHEET] 63 Ordering Codes Binary Page Mode Atmel Ordering Code AT45DB161E-SSHD2B-T 1 3 AT45DB161E-SHD2B-T 1 2 3 AT45DB161E-MHD2B-T 1 3 Package 8S1 8S2 1 8MA1 Lead Finish Operating Voltage NiPdAu 2.5V to 3.6V fSCK 85MHz Device Grade Industrial -40C to 85C AT45DB161E-SSHF2B-T 1 3 AT45DB161E-MHF2B-T 1 3 8S1 8MA1 NiPdAu 2.3V to 3.6V 85MHz Industrial -40C to 85C Notes The shipping carrier suffix is not marked on the device. Not recommended for new design. Use the 8S1 package option. Parts ordered with suffix and CAN# code ‘2B’ are shipped in tape and reel with the page size set to 512 bytes. This option is only available for shipping in T&R -T . 8S1 8S2 8MA1 Package Type 8-lead wide, Plastic Gull Wing Small Outline JEDEC SOIC 8-lead wide, Plastic Gull Wing Small Outline EIAJ SOIC 8-pad 5 x 6 x 0.6mm body , Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead UDFN Atmel AT45DB161E [PRELIMINARY DATASHEET] 64 Packaging Information 8S1 8-lead JEDEC SOIC TOP VIEW SIDE VIEW Notes This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. END VIEW COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOTE Package Drawing Contact 8S1, 8-lead Wide Body , Plastic Gull Wing Small Outline JEDEC SOIC Atmel AT45DB161E [PRELIMINARY DATASHEET] 65 8S2 8-lead EIAJ SOIC TOP VIEW END VIEW COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE SIDE VIEW Notes This drawing is for general information only refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between to mm. TITLE Package Drawing Contact 8S2, 8-lead, Body, Plastic Small Outline Package EIAJ Atmel AT45DB161E [PRELIMINARY DATASHEET] 66 8MA1 8-pad UDFN Pin 1 ID D

PDF Datasheet Preview

Atmel AT45DB161E
16-Mbits DataFlash with Extra 512-Kbits , 2.3V or 2.5V Minimum SPI Serial Flash Memory

PRELIMINARY DATASHEET

Single 2.3V - 3.6V or 2.5V - 3.6V supply

Serial Peripheral Interface SPI compatible Supports SPI modes 0 and 3 Supports RapidS operation

Continuous Read capability through entire array Up to 85MHz Low-power Read option up to 10MHz Clock-to-output time tV of 6ns maximum

User configurable page size 512 bytes per page 528 bytes per page default Page size can be factory pre-configured for 512 bytes

Two fully independent SRAM data buffers 512/528 bytes Allows receiving data while reprogramming the Main Memory Array

Flexible programming options Byte/Page program 1 to 512/528 bytes directly into main memory Buffer Write Buffer to Main Memory Page Program

Flexible Erase options Page Erase 512/528 bytes Block Erase 4KB Sector Erase 128KB Chip Erase 16-Mbits

Program and Erase Suspend/Resume

Advanced hardware and software data protection features Individual sector protection Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable OTP Security Register 64 bytes factory programmed with a unique identifier 64 bytes user programmable

Software controlled reset

JEDEC Standard Manufacturer and Device ID Read

Low-power dissipation 500nA Ultra-Deep Power-Down current typical 3uA Deep Power-Down current typical 25uA Standby current typical 11mA Active Read current typical

Endurance 100,000 program/erase cycles per page minimum

Data retention 20 years

Complies with full industrial temperature range

Green Pb/Halide-free/RoHS compliant packaging options 8-lead SOIC wide 8-pad Ultra-thin DFN 5 x 6 x 0.6mm 9-ball Chip-scale BGA 5 x 5 x 1.2mm

The Atmel AT45DB161E is a 2.3V or 2.5V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice, image, program code, and data storage applications. The AT45DB161E also supports RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organized as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB161E also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a system's ability to write a continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pademory, and E2PROM emulation bit or byte alterability can be easily handled with a self-contained three step read-modify-write operation.

Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the Atmel uses a serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage, and low-power are essential.

To allow for simple in-system re-programmability, the AT45DB161E does not require high input voltages for programming. The device operates from a single 2.3V to 3.6V or 2.5V to 3.6V power supply for the erase and program and read operations. The AT45DB161E is enabled through the Chip Select pin CS and accessed via a 3-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK .

All programming and erase cycles are self-timed.

Pin Configurations and Pinouts

Figure Pinouts
8-lead SOIC Top View

SI 1 SCK 2 RESET 3
8 SO 7 GND 6 VCC 5 WP
8-pad UDFN Top View

SI 1 SCK 2 RESET 3
8 SO 7 GND 6 VCC 5 WP
8-ball CBGA Top View

SCK GND VCC CS NC WP

SI RST

Note The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential. This pad can be a “no connect” or connected to GND.

Atmel AT45DB161E [PRELIMINARY DATASHEET]

Table Pin Configurations

Symbol CS SCK SI SO

RESET VCC GND

Name and Function
Devices are initially shipped from Atmel with the buffer and page sizes set to 528 bytes. Devices can be ordered from Atmel pre-configured for the "power of 2" binary size of 512 bytes. For details, see Section Ordering Information on page

To configure the device for "power of 2" binary page size 512 bytes , a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and A6h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed configuration process and nonvolatile register program cycle. The programming of the nonvolatile register should take place in a time of tEP, during which time the RDY/BUSY bit in the Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 512 bytes.

To configure the device for standard DataFlash page size 528 bytes , a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and A7h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initial the internally self-timed configuration process and nonvolatile register program cycle. The programming of the nonvolatile register should take place in a time of tEP, during which time the RDY/BUSY bit in the Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of the configuration process and register program cycle in order for the buffer and page size to be configured to 528 bytes.

Table Buffer and Page Size Configuration Commands

Command "Power of 2" binary page size 512 bytes DataFlash page size 528 bytes

Byte 1 3Dh

Byte 2 2Ah

Byte 3 80h

Byte 4 A6h A7h

Figure Buffer and Page Size Configuration

CS SI

Each transition represents eight bits

Opcode Byte 4

Atmel AT45DB161E [PRELIMINARY DATASHEET] 35

Manufacturer and Device ID Read

Identification information can be read from the device to enable systems to electronically query and identify the device while it is in the system. The identification method and the command opcode comply with the JEDEC Standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC-defined Manufacturer ID, the vendor-specific Device ID, and the vendor-specific Extended Device Information.

The Read Manufacturer and Device ID command is limited to a maximum clock frequency of fCLK. Since not all Flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the application can be identified properly. Once the identification process is complete, the application can then increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies.

To read the identification information, the CS pin must first be asserted and then the opcode 9Fh must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO during the subsequent clock cycles. The first byte to be output will be the Manufacturer ID, followed by two bytes of the Device ID information. The fourth byte output will be the Extended Device Information EDI String Length, which will be 01h indicating that one byte of EDI data follows. After the one byte of EDI data is output, the SO pin will go into a high-impedance state therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC Standard, reading the EDI String Length and any subsequent data is optional.

Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Table Manufacturer and Device ID Information

Byte No.

Data Type

Manufacturer ID

Device ID Byte 1

Device ID Byte 2
[Optional to Read] Extended Device Information EDI String Length
[Optional to Read] EDI Byte 1

Value 1Fh 26h 00h 01h 00h

Table Manufacturer and Device ID Details

Data Type

Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Details

Manufacturer ID

JEDEC Assigned Code
1Fh JEDEC code 0001 1111 1Fh for Atmel

Device ID Byte 1

Family Code

Density Code

Family code 001 AT45Dxxx Family Density code 00110 16-Mbit

Device ID Byte 2

Sub Code

Product Variant
Ordering Information
Ordering Detail

Atmel Designator

AT 4 5 D B 1 6 1 E - S F U - B

Product Family 45DB = Atmel DataFlash

Device Density 16 = 16-Mbit

Interface 1 = Serial

Shipping Carrier Option B = Bulk tubes T = Tape and reel Y = Trays

Device Grade H = Green, NiPdAu lead finish,

Industrial temperature range to +85°C U = Green, Matte Sn or Sn alloy, Industrial temperature range to +85°C

Operating Voltage D = 2.5V minimum 2.5V to 3.6V F = 2.3V minimum 2.3V to 3.6V

Package Option SS= 8-lead, wide SOIC S = 8-lead, wide SOIC M = 8-pad, 5 x 6 x 0.6mm UDFN CC= 9-ball, 3 x 3 1mm pitch CBGA

Atmel AT45DB161E [PRELIMINARY DATASHEET] 62
Ordering Codes
Atmel Ordering Code AT45DB161E-SSHD-B 1 AT45DB161E-SSHD-T 1 AT45DB161E-SHD-B 1 2 AT45DB161E-SHD-T 1 2 AT45DB161E-MHD-Y 1 AT45DB161E-MHD-T 1 AT45DB161E-CCUD-T

Package Lead Finish Operating Voltage
fSCK
8S2 8MA1 9C1

NiPdAu SnAgCu
2.5V to 3.6V
85MHz

AT45DB161E-SSHF-B 1 AT45DB161E-SSHF-T 1 AT45DB161E-SHF-B 1 2 AT45DB161E-SHF-T 1 2 AT45DB161E-MHF-Y 1 AT45DB161E-MHF-T 1
8S1 8S2 8MA1

NiPdAu
2.3V to 3.6V

Notes The shipping carrier suffix is not marked on the device. Not recommended for new design. Use the 8S1 package option.
85MHz

Device Grade

Industrial -40C to 85C

Industrial -40C to 85C
8S1 8S2 8MA1 9C1

Package Type 8-lead wide, Plastic Gull Wing Small Outline JEDEC SOIC 8-lead wide, Plastic Gull Wing Small Outline EIAJ SOIC 8-pad 5 x 6 x 0.6mm body , Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead UDFN 9-ball 3 x 3 array x 1mm pitch, Chip-scale Ball Grid Array CBGA

Atmel AT45DB161E [PRELIMINARY DATASHEET] 63
Ordering Codes Binary Page Mode
Atmel Ordering Code AT45DB161E-SSHD2B-T 1 3 AT45DB161E-SHD2B-T 1 2 3 AT45DB161E-MHD2B-T 1 3

Package 8S1 8S2 1 8MA1

Lead Finish Operating Voltage

NiPdAu
2.5V to 3.6V
fSCK 85MHz

Device Grade

Industrial -40C to 85C

AT45DB161E-SSHF2B-T 1 3 AT45DB161E-MHF2B-T 1 3
8S1 8MA1

NiPdAu
2.3V to 3.6V
85MHz

Industrial -40C to 85C

Notes The shipping carrier suffix is not marked on the device. Not recommended for new design. Use the 8S1 package option. Parts ordered with suffix and CAN# code ‘2B’ are shipped in tape and reel with the page size set to 512 bytes. This option is only available for shipping in T&R -T .
8S1 8S2 8MA1

Package Type 8-lead wide, Plastic Gull Wing Small Outline JEDEC SOIC 8-lead wide, Plastic Gull Wing Small Outline EIAJ SOIC 8-pad 5 x 6 x 0.6mm body , Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead UDFN

Atmel AT45DB161E [PRELIMINARY DATASHEET] 64

Packaging Information
8S1 8-lead JEDEC SOIC

TOP VIEW

SIDE VIEW

Notes This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

END VIEW

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN

NOTE

Package Drawing Contact 8S1, 8-lead Wide Body , Plastic Gull Wing Small Outline JEDEC SOIC

Atmel AT45DB161E [PRELIMINARY DATASHEET] 65
8S2 8-lead EIAJ SOIC

TOP VIEW

END VIEW

COMMON DIMENSIONS

Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

SIDE VIEW

Notes This drawing is for general information only refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between to mm.

TITLE Package Drawing Contact 8S2, 8-lead, Body, Plastic Small Outline Package EIAJ

Atmel AT45DB161E [PRELIMINARY DATASHEET] 66
8MA1 8-pad UDFN

Pin 1 ID D

More datasheets: 516-038 | 518-038 | FSBM20SL60 | 100NXXCAF | M43103 WH002 | M43103 WH005 | M43103 WH001 | 774 | QTLP650DRGBTR | AT45DB161E-SHD-T

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT45DB161E-MHD2B-T Datasheet file may be downloaded here without warranties.

Datasheet ID: AT45DB161E-MHD2B-T 519046