AT45DB081D-SSU-2.5 Datasheet

Atmel AT45DB081D

Part Datasheet
AT45DB081D-SSU-2.5 AT45DB081D-SSU-2.5 AT45DB081D-SSU-2.5 (pdf)
Related Parts Information
AT45DB081D-MU-2.5 AT45DB081D-MU-2.5 AT45DB081D-MU-2.5
AT45DB081D-SU-2.5 AT45DB081D-SU-2.5 AT45DB081D-SU-2.5
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• Single 2.5V or 2.7V to 3.6V Supply
• RapidS Serial Interface 66MHz Maximum Clock Frequency

SPI Compatible Modes 0 and 3
• User Configurable Page Size
256-Bytes per Page 264-Bytes per Page Size Can Be Factory Pre-configured for 256-Bytes
• Page Program Operation Intelligent Programming Operation 4,096 Pages 256/264-Bytes/Page Main Memory
• Flexible Erase Options Page Erase 256-Bytes Block Erase 2-Kbytes Sector Erase 64-Kbytes Chip Erase 8Mbits
• Two SRAM Data Buffers 256-/264-Bytes Allows Receiving of Data while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications
• Low-power Dissipation 7mA Active Read Current Typical 25µA Standby Current Typical 15µA Deep Power Down Typical
• Hardware and Software Data Protection Features Individual Sector
• Sector Lockdown for Secure Code and Data Storage Individual Sector
• Security 128-byte Security Register 64-byte User Programmable Space Unique 64-byte Device Identifier
• JEDEC Standard Manufacturer and Device ID Read
• 100,000 Program/Erase Cycles Per Page Minimum
• Data Retention 20 Years
• Industrial Temperature Range
• Green Pb/Halide-free/RoHS Compliant Packaging Options
8-megabit 2.5V or 2.7V Atmel DataFlash

Atmel AT45DB081D

The AT45DB081D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB081D supports Atmel RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies up to 66MHz. Its 8,650,752-bits of memory are organized as 4,096 pages of 256-bytes or 264-bytes each. In addition to the main memory, the AT45DB081D also contains two SRAM buffers of 256-/264-bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM emulation bit or byte alterability is easily handled with a self-contained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple

Atmel RapidS
address lines and a parallel interface, the uses an Atmel RapidS serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential.

To allow for simple in-system reprogrammability, the Atmel AT45DB081D does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB081D is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK .

All programming and erase cycles are self-timed.

Pin Configurations and Pinouts

Figure MLF VDFN Top View

8 SO 7 GND 6 VCC 5 WP

Figure SOIC Top View

8 SO 7 GND 6 VCC 5 WP

Note The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND
2 Atmel AT45DB081D

Atmel AT45DB081D

Table Symbol CS



Pin Configurations

Name and Function

Chip Select Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode not Deep Power-Down mode , and the output pin SO will be in a high-impedance state. When the device is deselected, data will not be accepted on the input pin SI . A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.

Serial Clock This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.

Serial Input The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.

Serial Output The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.

Write Protect When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register will be protected against program and erase operations regardless of whether the Enable Sector Protection command has been issued or not. The WP pin functions independently of the software controlled protection method. After the WP pin goes low, the content of the Sector Protection Register cannot be modified. If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore the command and perform no operation. The device will return to the idle state once the CS pin has been deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be recognized by the device when the WP pin is asserted. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible.

Reset A low state on the reset pin RESET will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally.

Device Power Supply The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted.

Ground The ground reference for the power supply. GND should be connected to the system ground.

Asserted State Type







“Power of 2” binary page size Configuration Register is a user-programmable nonvolatile register that allows the page size of the main memory to be configured for binary page size 256bytes or standard page size 264-bytes . The “power of 2” page size is a one-time programmable configuration register and once the device is configured for “power of 2” page size, it cannot be reconfigured again. The devices are initially shipped with the page size set to 264-bytes. The user has the option of ordering binary page size 256bytes devices from the factory. For details, please refer to Section ”Ordering Information” on page

For the binary “power of 2” page size to become effective, the following steps must be followed:

Program the one-time programmable configuration resister using opcode sequence 3DH, 2AH, 80H and A6H please see Section

Power cycle the device i.e. power down and power up again . User can now program the page for the binary page size. If the above steps are not followed in setting the page size prior to page programming, user may expect incorrect data during a read operation.

The address format will be changed after the device is configured for “power of 2” page size. See Section ”Command Sequence for Read/Write Operations for Page Size 256-Bytes Except Status Register Read, Manufacturer and Device ID Read ” on page

Programming the Configuration Register

To program the Configuration Register for “power of 2” binary page size, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Configuration Register should take place in a time of tP, during which time the Status Register will indicate that the device is busy. The device must be power-cycled after the completion of the program cycle to set the “power of 2” page size. If the device is powered-down before the completion of the program cycle, then setting the Configuration Register cannot be guaranteed. However, the user should check bit zero of the status register to see whether the page size was configured for binary page size. If not, the command can be re-issued again.

Table Programming the Configuration Register

Command Power of Two Page Size

Byte 1 3DH

Byte 2 2AH

Byte 3 80H

Byte 4 A6H

Figure Program Configuration Register CS

Opcode Byte 1

Each transition represents 8 bits

Opcode Byte 2

Opcode Byte 3

Opcode Byte 4

Manufacturer and Device ID Read

Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information.

To read the identification information, the CS pin must first be asserted and the opcode of 9FH must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00H indicating that no Extended Device Information follows. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional.

Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
24 Atmel AT45DB081D

Atmel AT45DB081D

Manufacturer and Device ID Information

Byte 1 Manufacturer ID

Hex Value

Bit 7 0

Bit 6 0

JEDEC Assigned Code

Bit 5 Bit 4 Bit 3 Bit 2

Bit 1

Bit 0 1

Byte 2 Device ID Part 1

Hex Value

Family Code

Bit 7 Bit 6 Bit 5

Bit 4 0

Density Code

Bit 3 Bit 2 Bit 1
Ordering Information
Ordering Code Detail AT 4 5DB0 8 SSU

Atmel Designator

Product Family

Device Density
8 = 8-megabit

1 = Serial

Device Grade

U = Matte Sn lead finish, industrial temperature range -40°C to +85°C

Package Option

M = 8-pad, 6 x 5 x 1mm MLF VDFN SS = 8-lead, wide SOIC S = 8-lead, wide SOIC

Green Package Options Pb/Halide-free/RoHS Compliant
Ordering Code 1 2

AT45DB081D-MU AT45DB081D-MU-SL954 3 AT45DB081D-MU-SL955 4

Package 8M1-A

Lead Finish Operating Voltage fSCK MHz Operation Range

AT45DB081D-SSU AT45DB081D-SSU-SL954 3 AT45DB081D-SSU-SL955 4

AT45DB081D-SU AT45DB081D-SU-SL954 3 AT45DB081D-SU-SL955 4

Matte Sn
2.7V to 3.6V

Industrial -40C to 85C



Matte Sn
2.5V to 3.6V


The shipping carrier option is not marked on the devices.

Standard parts are shipped with the page size set to 264-bytes. The user is able to configure these parts to a 256-byte page size if desired.

Parts ordered with suffix SL954 are shipped in bulk with the page size set to 256-bytes. Parts will have a 954 or SL954 marked on them.

Parts ordered with suffix SL955 are shipped in tape and reel with the page size set to 256-bytes. Parts will have a 954 or SL954 marked on them.
8M1-A 8S1 8S2

Package Type 8-pad, 6 x 5 x 1.00mm Body, Very Thin Dual Flat Package No Lead MLF VDFN 8-lead, Wide, Plastic Gull Wing Small Outline Package JEDEC SOIC 8-lead, Wide, Plastic Gull Wing Small Outline Package EIAJ SOIC

Packaging Information

Pin 1 ID


Pin #1 Notch


A3 A1

SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e L 0 K

COMMON DIMENSIONS Unit of Measure = mm



Package Drawing Contact:
8M1-A, 8-pad, 6 x 5 x 1.00mm Body, Thermally Enhanced Plastic Very Thin Dual Flat No Lead Package VDFN

48 Atmel AT45DB081D

Atmel AT45DB081D

Added part number ordering code details for suffixes SL954/955 Added ordering code details.

Changed tDIS Typ and Max to 27ns and 35ns, respectively.

Changed Deep Power-Down Current values - Increased typical value from 5µA to 15µA. - Increased maximum value from 15µA to25 µA.

L April 2009 M May 2010

Updated Absolute Maximum Ratings Removed Chip Erase Errata

Changed tSE Typ to and Max 5 to Changed tCE Typ TBD to 7 and Max TBD to 22 Changed from 10,000 to 20,000 cumulative page erase/program operations and added the please contact Atmel statement in section


No Errata Conditions
52 Atmel AT45DB081D


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More datasheets: IHSR36F2 | IHLR015XF6 | IHLR015XF2 | IHLR015XF1 | IHLR015XF3 | GWA-900-USB | AT45DB081D-SSU | AT45DB081D-MU-2.5 | AT45DB081D-MU | AT45DB081D-SU

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Datasheet ID: AT45DB081D-SSU-2.5 519042