AT45CS1282-TC

AT45CS1282-TC Datasheet

The AT45CS1282 is a 2.7-volt, dual-interface sequential access Flash memory

Part	Datasheet
AT45CS1282-TC	AT45CS1282-TC (pdf)

PDF Datasheet Preview
• Single 2.7V - 3.6V Supply • Dual-interface Architecture RapidS Serial Interface 50 MHz Maximum Clock Frequency SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz Rapid8 8-bit Interface 20 MHz Maximum Clock Frequency • Page Program 16,384 Pages 1,056 Bytes/Page Main Memory • Sector Erase Architecture Sixty-three 270,336-byte Sectors One 261,888-byte Sector One 8,488-byte Sector • Two 1056-byte SRAM Data Buffers Allows Receiving of Data while Reprogramming the Flash Array • Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications • Low-power Dissipation 10 mA Active Read Current Typical Serial Interface 12 mA Active Read Current Typical 8-bit Interface 15 µA CMOS Standby Current Typical • Hardware Data Protection • Security 128-byte Security Register 64-byte User Programmable Space Unique 64-byte Device Identifier • JEDEC Standard Manufacturer and Device ID Read • 100 Program/Erase Cycles Per Sector Minimum • Data Retention 10 Years • Commercial Temperature Range The AT45CS1282 is a 2.7-volt, dual-interface sequential access Flash memory ideally suited for infrequent code shadowing applications. This device utilizes Atmel’s e-STAC Multi-Level Cell MLC memory technology, which allows a single cell to Pin Configurations Pin Name CS SCK/CLK SI SO I/O7 - I/O0 RESET RDY/BUSY SER/BYTE Function Chip Select Serial Clock/Clock Serial Input Serial Output 8-bit Input/Output Hardware Page Write Protect Pin Chip Reset Ready/Busy Serial/8-bit Interface Control Note: Optional Use See pin description text for connection information. TSOP Top View Type 1 NC 1 NC 2 RDY/BUSY 3 RESET 4 WP 5 NC 6 NC 7 NC 8 VCC 9 GND 10 NC 11 NC 12 NC 13 NC 14 CS 15 SCK 16 SI 17 SO* 18 NC 19 NC 20 40 NC 39 NC 38 NC 37 NC 36 NC 35 I/O7* 34 I/O6* 33 I/O5* 32 I/O4* 31 VCCP* 30 GNDP* 29 I/O3* 28 I/O2* 27 I/O1* 26 I/O0* 25 SER/BYTE* 24 CLK 23 NC 22 NC 21 NC CBGA Top View 1 23 45 C NC SER/BYTE NC I/O7 I/O6 D I/O2 SCK/CLK GND VCC I/O5 E I/O1 CS RDY/BUSY WP I/O4 F I/O0 SO SI RESET I/O3 G NC GNDP VCCP NC 128-megabit 2.7-volt Dual-interface Code Shadow AT45CS1282 Preliminary Block Diagram Memory Array store two bits of information delivering a very cost effective high density Flash memory. The AT45CS1282 supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial interface is SPI compatible for frequencies up to 33 MHz. The dual-interface allows a dedicated serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller or vice versa. However, the use of either interface is purely optional. Its 138,412,032 bits of memory are organized as 16,384 pages of 1,056 bytes each. In addition to the 132-megabit main memory, the AT45CS1282 also contains two SRAM buffers of 1,056 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses either a RapidS serial interface or a 8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial applications where high-density, low-pin count, low-voltage and low-power are essential. The device operates at clock frequencies up to 50 MHz with a typical active read current consumption of 10 mA. To allow for simple in-system reprogrammability, the AT45CS1282 does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45CS1282 is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK , or an 8-bit interface consisting of the input/output pins I/O7 - I/O0 and the clock pin CLK . All programming and erase cycles are self-timed. FLASH MEMORY ARRAY PAGE 1056 BYTES SCK/CLK CS RESET VCC GND RDY/BUSY SER/BYTE BUFFER 1 1056 BYTES BUFFER 2 1056 BYTES I/O INTERFACE SI SO I/O7 - I/O0 To provide optimal flexibility, the memory array of the AT45CS1282 is divided into two levels of granularity comprising of sectors, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector. All program operations to the DataFlash occur on a page by page basis. The erase operations is performed at the sector level. 2 AT45CS1282 [Preliminary] Ordering Information fSCK MHz ICC mA Active Standby Ordering Code AT45CS1282-TC Note RapidS Serial Interface. AT45CS1282-CC Package 40T 44C2 Operation Range Commercial 0° C to 70° C Commercial 0° C to 70° C 40T 44C2 Package Type 40-lead, 10 x 20 mm Plastic Thin Small Outline Package, Type I TSOP 44-ball, 8 x 12 mm Plastic Chip-size Ball Grid Array Package CBGA 30 AT45CS1282 [Preliminary] Packaging Information 40T TSOP PIN 1 AT45CS1282 [Preliminary] 0º ~ 8º c Pin 1 Identifier SEATING PLANE GAGE PLANE This package conforms to JEDEC reference MO-142, Variation CD. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 D D1 E L L1 b c e MIN NOM MAX BASIC BASIC NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 40T, 40-lead 10 x 20 mm Package Plastic Thin Small Outline Package, Type I TSOP 10/18/01 44C2 CBGA Marked A1 Identifier C Seating Plane Side View Top View 5 432 1 A1 Ball Corner Bottom View COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 D D1 E E1 e Øb NOTE

PDF Datasheet Preview

• Single 2.7V - 3.6V Supply
• Dual-interface Architecture

RapidS Serial Interface 50 MHz Maximum Clock Frequency SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz

Rapid8 8-bit Interface 20 MHz Maximum Clock Frequency
• Page Program
16,384 Pages 1,056 Bytes/Page Main Memory
• Sector Erase Architecture

Sixty-three 270,336-byte Sectors One 261,888-byte Sector One 8,488-byte Sector
• Two 1056-byte SRAM Data Buffers Allows Receiving of Data while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications
• Low-power Dissipation 10 mA Active Read Current Typical Serial Interface 12 mA Active Read Current Typical 8-bit Interface 15 µA CMOS Standby Current Typical
• Hardware Data Protection
• Security 128-byte Security Register 64-byte User Programmable Space Unique 64-byte Device Identifier
• JEDEC Standard Manufacturer and Device ID Read
• 100 Program/Erase Cycles Per Sector Minimum
• Data Retention 10 Years
• Commercial Temperature Range

The AT45CS1282 is a 2.7-volt, dual-interface sequential access Flash memory
ideally suited for infrequent code shadowing applications. This device utilizes Atmel’s e-STAC Multi-Level Cell MLC memory technology, which allows a single cell to

Pin Configurations

Pin Name CS SCK/CLK SI SO I/O7 - I/O0

RESET RDY/BUSY

SER/BYTE

Function Chip Select Serial Clock/Clock Serial Input Serial Output 8-bit Input/Output Hardware Page Write Protect Pin Chip Reset Ready/Busy Serial/8-bit Interface Control

Note:
*Optional Use See pin description text for connection information.

TSOP Top View Type 1

NC 1 NC 2 RDY/BUSY 3 RESET 4 WP 5 NC 6 NC 7 NC 8 VCC 9 GND 10 NC 11 NC 12 NC 13 NC 14 CS 15 SCK 16 SI* 17 SO* 18 NC 19 NC 20
40 NC 39 NC 38 NC 37 NC 36 NC 35 I/O7* 34 I/O6* 33 I/O5* 32 I/O4* 31 VCCP* 30 GNDP* 29 I/O3* 28 I/O2* 27 I/O1* 26 I/O0* 25 SER/BYTE* 24 CLK 23 NC 22 NC 21 NC

CBGA Top View
1 23 45

C NC SER/BYTE NC I/O7 I/O6

D I/O2 SCK/CLK GND VCC I/O5

E I/O1 CS RDY/BUSY WP I/O4

F I/O0 SO SI RESET I/O3

G NC GNDP VCCP NC
128-megabit 2.7-volt Dual-interface Code Shadow AT45CS1282 Preliminary

Block Diagram Memory Array
store two bits of information delivering a very cost effective high density Flash memory. The AT45CS1282 supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial interface is SPI compatible for frequencies up to 33 MHz. The dual-interface allows a dedicated serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller or vice versa. However, the use of either interface is purely optional. Its 138,412,032 bits of memory are organized as 16,384 pages of 1,056 bytes each. In addition to the 132-megabit main memory, the AT45CS1282 also contains two SRAM buffers of 1,056 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses either a RapidS serial interface or a 8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial applications where high-density, low-pin count, low-voltage and low-power are essential. The device operates at clock frequencies up to 50 MHz with a typical active read current consumption of 10 mA.

To allow for simple in-system reprogrammability, the AT45CS1282 does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45CS1282 is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK , or an 8-bit interface consisting of the input/output pins I/O7 - I/O0 and the clock pin CLK .

All programming and erase cycles are self-timed.

FLASH MEMORY ARRAY

PAGE 1056 BYTES

SCK/CLK CS

RESET VCC GND

RDY/BUSY SER/BYTE

BUFFER 1 1056 BYTES

BUFFER 2 1056 BYTES

I/O INTERFACE

SI SO

I/O7 - I/O0

To provide optimal flexibility, the memory array of the AT45CS1282 is divided into two levels of granularity comprising of sectors, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector. All program operations to the DataFlash occur on a page by page basis. The erase operations is performed at the sector level.
2 AT45CS1282 [Preliminary]
Ordering Information
fSCK MHz

ICC mA Active Standby
Ordering Code

AT45CS1282-TC

Note RapidS Serial Interface.

AT45CS1282-CC

Package
40T 44C2

Operation Range Commercial 0° C to 70° C Commercial 0° C to 70° C
40T 44C2

Package Type 40-lead, 10 x 20 mm Plastic Thin Small Outline Package, Type I TSOP 44-ball, 8 x 12 mm Plastic Chip-size Ball Grid Array Package CBGA
30 AT45CS1282 [Preliminary]

Packaging Information
40T TSOP

PIN 1

AT45CS1282 [Preliminary]
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation CD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

BASIC

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
40T, 40-lead 10 x 20 mm Package Plastic Thin Small Outline Package, Type I TSOP
10/18/01
44C2 CBGA

Marked A1 Identifier

C Seating Plane

Side View

Top View
5 432 1

A1 Ball Corner

Bottom View

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 D D1 E E1 e Øb

NOTE

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Datasheet ID: AT45CS1282-TC 519034