AT29LV512-15TI

AT29LV512-15TI Datasheet


The AT29LV512 is a 3-volt-only in-system Flash programmable erasable read-only memory PEROM . Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 54 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 40 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

Part Datasheet
AT29LV512-15TI AT29LV512-15TI AT29LV512-15TI (pdf)
Related Parts Information
AT29LV512-15JC AT29LV512-15JC AT29LV512-15JC
AT29LV512-15JI AT29LV512-15JI AT29LV512-15JI
AT29LV512-15TC AT29LV512-15TC AT29LV512-15TC
AT29LV512-20TC AT29LV512-20TC AT29LV512-20TC
AT29LV512-20TI AT29LV512-20TI AT29LV512-20TI
AT29LV512-25JC AT29LV512-25JC AT29LV512-25JC
AT29LV512-25JI AT29LV512-25JI AT29LV512-25JI
AT29LV512-25TC AT29LV512-25TC AT29LV512-25TC
AT29LV512-20JC AT29LV512-20JC AT29LV512-20JC
AT29LV512-25TI AT29LV512-25TI AT29LV512-25TI
AT29LV512-20JI AT29LV512-20JI AT29LV512-20JI
AT29LV512-12JI AT29LV512-12JI AT29LV512-12JI
AT29LV512-12TC AT29LV512-12TC AT29LV512-12TC
AT29LV512-12TI AT29LV512-12TI AT29LV512-12TI
AT29LV512-12JC AT29LV512-12JC AT29LV512-12JC
PDF Datasheet Preview
• Single Supply Voltage, Range 3V to 3.6V
• 3-volt Only Read and Write Operation
• Software Protected Programming
• Low-power Dissipation
15 mA Active Current 40 µA CMOS Standby Current
• Fast Read Access Time 120 ns
• Sector Program Operation Single-cycle Reprogram Erase and Program 512 Sectors 128 Bytes/Sector Internal Address and Data Latches for 128 Bytes
• Fast Sector Program Cycle Time 20 ms Max.
• Internal Program Control and Timer
• DATA Polling for End of Program Detection
• Typical Endurance > 10,000 Cycles
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges

The AT29LV512 is a 3-volt-only in-system Flash programmable erasable read-only memory PEROM . Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 54 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 40 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.
512K 64K x 8 3-volt Only Flash Memory

AT29LV512

Pin Configurations

Pin Name

Function

A0 - A15 CE

Addresses Chip Enable

OE WE I/O0 - I/O7 NC

Output Enable Write Enable Data Inputs/Outputs No Connect

PLCC Top View
4 A12 3 A15 2 NC 1 NC 32 VCC 31 WE 30 NC

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

TSOP Top View Type 1

A11 1 A9 2 A8 3

A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 NC 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20

Block Diagram

To allow for simple in-system reprogrammability, the AT29LV512 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29LV512 is performed on a sector basis 128 bytes of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are captured at microprocessor speed and internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.

Device Operation

READ The AT29LV512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

SOFTWARE DATA PROTECTION PROGRAMMING The AT29LV512 has 512 individual sectors, each 128 bytes. Using the software data protection feature, byte loads are used to enter the 128 bytes of a sector to be programmed. The AT29LV512 can only be programmed or reprogrammed using the software data protection feature. The device is programmed on a sector basis. If a byte of data within the sector is to be changed, data for the entire 128-byte sector must be loaded into the device. The AT29LV512 automatically does a sector erase prior to loading the data into the sector. An erase command is not required.

Software data protection protects the device from inadvertent programming. A series of three program commands to specific addresses with specific data must be presented to the device before programming may occur. After writing the three-byte command sequence and after tWC , the entire device is protected. The same three program commands must begin each program operation. All software program commands must obey the sector program timing specifications. Power transitions will not reset the software data protection feature however, the software feature will guard against inadvertent program cycles during power transitions.
2 AT29LV512

AT29LV512

Any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device however, for the duration of tWC, a read operation will effectively be a polling operation. After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

The 128 bytes of data must be loaded into each sector. Any byte that is not loaded during the programming of its sector will be erased to read FFh. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high-to-low transition on WE or CE within 150 µs of the low-to-high transition of WE or CE of the preceding byte. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition, the load period will end and the internal programming period will start. A7 to A15 specify the sector address. The sector address must be valid during each high-to-low transition of WE or CE . A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.

HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT29LV512 in the following ways a VCC sense if VCC is below 1.8V typical , the program function is inhibited b VCC power on delay once VCC has reached the VCC sense level, the device will automatically time out 10 ms typical before programming c Program inhibit holding any one of OE low, CE high or WE high inhibits program cycles and d Noise filter pulses of less than 15 ns typical on the WE or CE inputs will not initiate a program cycle.

INPUT LEVELS While operating with a 3.3V ±10% power supply, the address inputs and control inputs OE, CE and WE may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to volts.

PRODUCT IDENTIFICATION The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part i.e., using the device code , and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size.

For details, see Operating Modes for hardware operation or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING The AT29LV512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.

TOGGLE BIT In addition to DATA polling the AT29LV512 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.

Absolute Maximum Ratings*
Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT29LV512-12JC AT29LV512-12TC AT29LV512-12JI AT29LV512-12TI AT29LV512-15JC AT29LV512-15TC AT29LV512-15JI AT29LV512-15TI AT29LV512-20JC AT29LV512-20TC AT29LV512-20JI AT29LV512-20TI AT29LV512-25JC AT29LV512-25TC AT29LV512-25JI AT29LV512-25TI

Note:

Not recommended for New Designs.

AT29LV512

Package 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T

Operation Range

Commercial 0° to 70°C

Industrial -40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C

Package Type
32-lead, Plastic J-leaded Chip Carrier PLCC
32-lead, Thin Small Outline Package TSOP

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
12 AT29LV512
32T TSOP

AT29LV512

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation BD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e
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Datasheet ID: AT29LV512-15TI 519008