AT29C512-90PC

AT29C512-90PC Datasheet


The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only memory PEROM . Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

Part Datasheet
AT29C512-90PC AT29C512-90PC AT29C512-90PC (pdf)
Related Parts Information
AT29C512-70JC AT29C512-70JC AT29C512-70JC
AT29C512-70JI AT29C512-70JI AT29C512-70JI
AT29C512-70PC AT29C512-70PC AT29C512-70PC
AT29C512-70TC AT29C512-70TC AT29C512-70TC
AT29C512-70TI AT29C512-70TI AT29C512-70TI
AT29C512-12JI AT29C512-12JI AT29C512-12JI
AT29C512-15PC AT29C512-15PC AT29C512-15PC
AT29C512-12TC AT29C512-12TC AT29C512-12TC
AT29C512-15JI AT29C512-15JI AT29C512-15JI
AT29C512-15JC AT29C512-15JC AT29C512-15JC
AT29C512-12PI AT29C512-12PI AT29C512-12PI
AT29C512-12PC AT29C512-12PC AT29C512-12PC
AT29C512-12JC AT29C512-12JC AT29C512-12JC
AT29C512-15PI AT29C512-15PI AT29C512-15PI
AT29C512-12TI AT29C512-12TI AT29C512-12TI
AT29C512-15TC AT29C512-15TC AT29C512-15TC
AT29C512-15TI AT29C512-15TI AT29C512-15TI
AT29C512-90JC AT29C512-90JC AT29C512-90JC
AT29C512-90JI AT29C512-90JI AT29C512-90JI
AT29C512-90TC AT29C512-90TC AT29C512-90TC
AT29C512-90TI AT29C512-90TI AT29C512-90TI
AT29C512-90PI AT29C512-90PI AT29C512-90PI
PDF Datasheet Preview
• Fast Read Access Time 70 ns
• 5-volt Only Reprogramming
• Sector Program Operation

Single Cycle Reprogram Erase and Program
512 Sectors 128 Bytes/Sector

Internal Address and Data Latches for 128 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Sector Program Cycle Time 10 ms
• DATA Polling for End of Program Detection
• Low Power Dissipation
50 mA Active Current 100 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges

The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only memory PEROM . Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

Pin Configurations

Pin Name A0 - A15 CE OE WE I/O0 - I/O7 NC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect

TSOP Top View Type 1

DIP Top View

NC 1 NC 2 A15 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16
32 VCC 31 WE 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3

A11 1 A9 2 A8 3

A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 NC 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3

PLCC Top View
4 A12 3 A15 2 NC 1 NC 32 VCC 31 WE 30 NC

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7
512K 64K x 8 5-volt Only Flash Memory AT29C512

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20

Block Diagram

To allow for simple in-system reprogrammability, the AT29C512 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C512 is performed on a sector basis 128 bytes of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.

Device Operation

READ The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

BYTE LOAD Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

PROGRAM The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high-to-low transition on WE or CE within 150 µs of the low-to-high transition of WE or CE of the preceding byte. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition, the load period will end and the internal programming period will start. A7 to A15 specify the sector address. The sector address must be valid during each high-to-low transition of WE or CE . A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.
2 AT29C512

AT29C512

SOFTWARE DATA PROTECTION A software controlled data protection feature is available on the AT29C512. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature however, the software feature will guard against inadvertent program cycles during power transitions. Once set, software data protection will remain active unless the disable command sequence is issued. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device however, for the duration of tWC, a read operation will effectively be a polling operation. After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT29C512 in the following ways a VCC sense if VCC is below 3.8V typical , the program function is inhibited b VCC power on delay once VCC has reached the VCC sense level, the device will automatically time out 5 ms typical before programming c Program inhibit holding any one of OE low, CE high or WE high inhibits program cycles and d Noise filter pulses of less than 15 ns typical on the WE or CE inputs will not initiate a program cycle. PRODUCT IDENTIFICATION The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part i.e., using the device code , and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size. For details, see Operating Modes for hardware operation or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING The AT29C512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.

TOGGLE BIT In addition to DATA polling the AT29C512 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature -65°C to +150°C

All Input Voltages including NC Pins with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V
Ordering Information
tACC ns 70

Note:

ICC mA

Active

Standby
Ordering Code

AT29C512-70JC

AT29C512-70PC

AT29C512-70TC

AT29C512-70JI

AT29C512-70TI

AT29C512-90JC

AT29C512-90PC

AT29C512-90TC

AT29C512-90JI

AT29C512-90PI

AT29C512-90TI

AT29C512-12JC

AT29C512-12PC

AT29C512-12TC

AT29C512-12JI

AT29C512-12PI

AT29C512-12TI

AT29C512-15JC

AT29C512-15PC

AT29C512-15TC

AT29C512-15JI

AT29C512-15PI

AT29C512-15TI

Not recommended for New Designs.

Package
32J 32P6 32T
32J 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T

Operation Range Commercial 0° to 70°C

Industrial -40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C
More datasheets: AT29C512-15JC | AT29C512-12PI | AT29C512-12PC | AT29C512-12JC | AT29C512-15PI | AT29C512-12TI | AT29C512-15TC | AT29C512-15TI | AT29C512-90JC | AT29C512-90JI


Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT29C512-90PC Datasheet file may be downloaded here without warranties.

Datasheet ID: AT29C512-90PC 518999