AT29C257-90JC

AT29C257-90JC Datasheet

AT29C257

Part	Datasheet
AT29C257-90JC	AT29C257-90JC (pdf)

Related Parts	Information
AT29C257-15JI	AT29C257-15JI
AT29C257-12JC	AT29C257-12JC
AT29C257-12JI	AT29C257-12JI
AT29C257-15JC	AT29C257-15JC
AT29C257-70JC	AT29C257-70JC
AT29C257-90JI	AT29C257-90JI
AT29C257-70JI	AT29C257-70JI
AT29C257-90JI-T	AT29C257-90JI-T
AT29C257-12JC-T	AT29C257-12JC-T
AT29C257-12JI-T	AT29C257-12JI-T
AT29C257-15JC-T	AT29C257-15JC-T
AT29C257-70JC-T	AT29C257-70JC-T
AT29C257-70JI-T	AT29C257-70JI-T
AT29C257-90JC-T	AT29C257-90JC-T

PDF Datasheet Preview
AT29C257 Fast Read Access Time - 70 ns • 5-Volt-Only Reprogramming • Page Program Operation Single Cycle Reprogram Erase and Program Internal Address and Data Latches for 64-Bytes Internal Program Control and Timer • Hardware and Software Data Protection • Fast Program Cycle Times Page 64-Byte Program Time - 10 ms Chip Erase Time - 10 ms DATA Polling for End of Program Detection • Low Power Dissipation 50 mA Active Current 300 µA CMOS Standby Current Typical Endurance > 10,000 Cycles • Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs • Pin-Compatible with AT29C010A and AT29C512 for Easy System Upgrades 256K 32K x 8 5-volt Only CMOS Flash Memory The AT29C257 is a 5-volt-only in-system Flash programmable and erasable read only memory PEROM . Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW. When the device is deselected, the CMOS standby current is less than 300 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. To allow for simple in-system reprogrammability, the AT29C257 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from a static RAM. Reprogramming the AT29C257 is performed on a page basis 64-bytes of data are loaded into the device and then simultaneously programmed. The contents of the entire device may be erased by using a 6-byte software code although erasure before programming is not needed . During a reprogram cycle, the address locations and 64-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the page and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected a new access for a read, program or chip erase can begin. AT29C257 Pin Configurations Pin Name Function A0 - A14 Addresses Chip Enable Output Enable Write Enable I/O0 - I/O7 Data Inputs/Outputs No Connect Don’t Connect PLCC Top View 0012K 4-105 Block Diagram Device Operation READ The AT29C257 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention. BYTE LOAD A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Byte loads are used to enter the 64-bytes of a page to be programmed or the software codes for data protection and chip erasure. PROGRAM The device is reprogrammed on a page basis. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded during the programming of its page will be indeterminate. Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE or CE within 150 µs of the low to high transition of WE or CE of the preceding byte. If a high to low transition is not detected within 150 µs of the last low to high transition, the load period will end and the internal programming period will start. A6 to A14 specify the page address. The page address must be valid during each high to low transition of WE or CE . A0 to A5 specify the byte address within the page. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation. SOFTWARE DATA PROTECTION A software controlled data protection feature is available on the AT29C257. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the page program timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions. Once set, software data protection will remain active unless the disable command sequence is issued. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device however, for the duration of tWC, a read operation will effectively be a polling operation. After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 64-bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. continued 4-106 AT29C257 AT29C257 Device Operation Continued HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT29C257 in the following ways a VCC if VCC is below 3.8V typical , the program function is inhibited. b VCC power on once VCC has reached the VCC sense level, the device will automatically time out 5 ms typical before programming. c Program holding any one of OE low, CE high or WE high inhibits program cycles. d Noise pulses of less than 15 ns typical on the WE or CE inputs will not initiate a program cycle. Ordering Information tACC ns ICC mA Active Standby Ordering Code AT29C257-70JC AT29C257-70JI AT29C257-90JC AT29C257-90JI AT29C257-12JC AT29C257-12JI AT29C257-15JC AT29C257-15JI Package 32J Operation Range Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C 32J 4-116 Package Type 32 Lead, Plastic J-Leaded Chip Carrier PLCC AT29C257

PDF Datasheet Preview

AT29C257

Fast Read Access Time - 70 ns
• 5-Volt-Only Reprogramming
• Page Program Operation

Single Cycle Reprogram Erase and Program Internal Address and Data Latches for 64-Bytes Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Program Cycle Times

Page 64-Byte Program Time - 10 ms Chip Erase Time - 10 ms DATA Polling for End of Program Detection
• Low Power Dissipation 50 mA Active Current 300 µA CMOS Standby Current Typical Endurance > 10,000 Cycles
• Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs
• Pin-Compatible with AT29C010A and AT29C512 for Easy System Upgrades
256K 32K x 8 5-volt Only CMOS Flash Memory

The AT29C257 is a 5-volt-only in-system Flash programmable and erasable read only memory PEROM . Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW. When the device is deselected, the CMOS standby current is less than 300 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29C257 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from a static RAM. Reprogramming the AT29C257 is performed on a page basis 64-bytes of data are loaded into the device and then simultaneously programmed. The contents of the entire device may be erased by using a 6-byte software code although erasure before programming is not needed .

During a reprogram cycle, the address locations and 64-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the page and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected a new access for a read, program or chip erase can begin.

AT29C257

Pin Configurations

Pin Name Function

A0 - A14 Addresses

Chip Enable

Output Enable

Write Enable

I/O0 - I/O7 Data Inputs/Outputs

No Connect

Don’t Connect

PLCC Top View
0012K
4-105

Block Diagram

Device Operation

READ The AT29C257 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention.

BYTE LOAD A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Byte loads are used to enter the 64-bytes of a page to be programmed or the software codes for data protection and chip erasure.

PROGRAM The device is reprogrammed on a page basis. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded during the programming of its page will be indeterminate. Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE or CE within 150 µs of the low to high transition of WE or CE of the preceding byte. If a high to low transition is not detected within 150 µs of the last low to high transition, the load period will end and the internal programming period will start. A6 to A14 specify the page address. The page address must be valid during each high to low transition of WE or CE . A0 to A5 specify the byte address within the page. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.

SOFTWARE DATA PROTECTION A software controlled data protection feature is available on the AT29C257. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the page program timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

Once set, software data protection will remain active unless the disable command sequence is issued.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device however, for the duration of tWC, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 64-bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation.
continued
4-106

AT29C257

AT29C257

Device Operation Continued

HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT29C257 in the following ways a VCC if VCC is below 3.8V typical , the program function is inhibited. b VCC power on once VCC has reached the VCC sense level, the device will automatically time out 5 ms typical before programming. c Program holding any one of OE low, CE high or WE high inhibits program cycles. d Noise pulses of less than 15 ns typical on the WE or CE inputs will not initiate a program cycle.
Ordering Information
tACC ns

ICC mA

Active Standby
Ordering Code AT29C257-70JC AT29C257-70JI AT29C257-90JC AT29C257-90JI AT29C257-12JC AT29C257-12JI AT29C257-15JC AT29C257-15JI

Package 32J

Operation Range

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C
32J 4-116

Package Type 32 Lead, Plastic J-Leaded Chip Carrier PLCC

AT29C257

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Datasheet ID: AT29C257-90JC 518997