AT29C256-15TI

AT29C256-15TI Datasheet


The AT29C256 is a five-volt-only in-system Flash programmable and erasable read only memory PEROM . Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW. When the device is deselected, the CMOS standby current is less than 300 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

Part Datasheet
AT29C256-15TI AT29C256-15TI AT29C256-15TI (pdf)
Related Parts Information
AT29C256-90PI AT29C256-90PI AT29C256-90PI
AT29C256-12JI AT29C256-12JI AT29C256-12JI
AT29C256-12PC AT29C256-12PC AT29C256-12PC
AT29C256-12PI AT29C256-12PI AT29C256-12PI
AT29C256-12TC AT29C256-12TC AT29C256-12TC
AT29C256-15JC AT29C256-15JC AT29C256-15JC
AT29C256-90TI AT29C256-90TI AT29C256-90TI
AT29C256-15PC AT29C256-15PC AT29C256-15PC
AT29C256-15PI AT29C256-15PI AT29C256-15PI
AT29C256-15TC AT29C256-15TC AT29C256-15TC
AT29C256-90TC AT29C256-90TC AT29C256-90TC
AT29C256-90JC AT29C256-90JC AT29C256-90JC
AT29C256-12JC AT29C256-12JC AT29C256-12JC
AT29C256-90PC AT29C256-90PC AT29C256-90PC
AT29C256-12TI AT29C256-12TI AT29C256-12TI
AT29C256-90JI AT29C256-90JI AT29C256-90JI
AT29C256-70JC AT29C256-70JC AT29C256-70JC
AT29C256-70JI AT29C256-70JI AT29C256-70JI
AT29C256-70PC AT29C256-70PC AT29C256-70PC
AT29C256-70PI AT29C256-70PI AT29C256-70PI
AT29C256-70TC AT29C256-70TC AT29C256-70TC
AT29C256-70TI AT29C256-70TI AT29C256-70TI
AT29C256-15JI AT29C256-15JI AT29C256-15JI
AT29C256-90JI-T AT29C256-90JI-T AT29C256-90JI-T
AT29C256-90JC-T AT29C256-90JC-T AT29C256-90JC-T
AT29C256-90TC-T AT29C256-90TC-T AT29C256-90TC-T
AT29C256-70TI-T AT29C256-70TI-T AT29C256-70TI-T
AT29C256-70TC-T AT29C256-70TC-T AT29C256-70TC-T
AT29C256-70JC-T AT29C256-70JC-T AT29C256-70JC-T
AT29C256-12TI-T AT29C256-12TI-T AT29C256-12TI-T
AT29C256-90TI-T AT29C256-90TI-T AT29C256-90TI-T
AT29C256-12TC-T AT29C256-12TC-T AT29C256-12TC-T
AT29C256-12JI-T AT29C256-12JI-T AT29C256-12JI-T
AT29C256-12JC-T AT29C256-12JC-T AT29C256-12JC-T
AT29C256-70JI-T AT29C256-70JI-T AT29C256-70JI-T
PDF Datasheet Preview
• Fast Read Access Time 70 ns
• 5-volt Only Reprogramming
• Page Program Operation

Single Cycle Reprogram Erase and Program Internal Address and Data Latches for 64 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Program Cycle Times Page 64 Byte Program Time 10 ms Chip Erase 10 ms
• DATA Polling for End of Program Detection
• Low-power Dissipation 50 mA Active Current 300 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges

The AT29C256 is a five-volt-only in-system Flash programmable and erasable read only memory PEROM . Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW. When the device is deselected, the CMOS standby current is less than 300 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.
256K 32K x 8 5-volt Only Flash Memory

AT29C256

Pin Configurations

Pin Name A0 - A14 CE

Function Addresses Chip Enable

OE WE I/O0 - I/O7

Output Enable Write Enable Data Inputs/Outputs

No Connect

Don’t Connect

PLCC and LCC Top View
4 A7 3 A12 2 WE 1 DC 32 VCC 31 A14 30 A13

A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13
29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6

I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20

Note PLCC package pins 1 and 17 are DON’T CONNECT.

DIP Top View

WE 1 A12 2

A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC 27 A14 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3

TSOP Top View Type 1

OE 22 A11 23

A9 24 A8 25 A13 26 A14 27 VCC 28 WE 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7
21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 14 GND 13 I/O2 12 I/O1 11 I/O0 10 A0
9 A1 8 A2

Block Diagram

To allow for simple in-system reprogrammability, the AT29C256 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from a static RAM. Reprogramming the AT29C256 is performed on a page basis 64 bytes of data are loaded into the device and then simultaneously programmed. The contents of the entire device may be erased by using a six-byte software code although erasure before programming is not needed .

During a reprogram cycle, the address locations and 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the page and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected a new access for a read, program or chip erase can begin.

Device Operation

READ The AT29C256 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

BYTE LOAD A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the software codes for data protection and chip erasure.
2 AT29C256

AT29C256

PROGRAM The device is reprogrammed on a page basis. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded during the programming of its page will be indeterminate. Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high-to-low transition on WE or CE within 150 µs of the low-tohigh transition of WE or CE of the preceding byte. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition, the load period will end and the internal programming period will start. A6 to A14 specify the page address. The page address must be valid during each high-to-low transition of WE or CE . A0 to A5 specify the byte address within the page. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation. SOFTWARE DATA PROTECTION A software controlled data protection feature is available on the AT29C256. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the page program timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

Once set, software data protection will remain active unless the disable command sequence is issued.

After setting SDP, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device however, for the duration of tWC, a read operation will effectively be a polling operation. After the software data protection’s three-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 64 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation.

HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT29C256 in the following ways a VCC sense if VCC is below 3.8V typical , the program function is inhibited b VCC power on delay once VCC has reached the VCC sense level, the device will automatically time out 5 ms typical before programming c Program inhibit holding any one of OE low, CE high or WE high inhibits program cycles and d Noise filter pulses of less than 15 ns typical on the WE or CE inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION The product identification mode identifies the device and manufacturer and may be accessed by a hardware operation. For details, see Operating Modes or Product Identification.

DATA POLLING The AT29C256 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.
Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code

AT29C256-70JC AT29C256-70PC AT29C256-70TC

AT29C256-70JI AT29C256-70TI AT29C256-90JC AT29C256-90PC AT29C256-90TC AT29C256-90JI AT29C256-90PI AT29C256-90TI AT29C256-12JC AT29C256-12PC AT29C256-12TC

AT29C256-12JI AT29C256-12PI AT29C256-12TI

AT29C256-15JC AT29C256-15PC AT29C256-15TC

AT29C256-15JI AT29C256-15PI AT29C256-15TI

Note:

Not recommended for New Designs.

Package
32J 28P6 28T
32J 28T 32J 28P6 28T 32J 28P6 28T 32J 28P6 28T
32J 28P6 28T
32J 28P6 28T
32J 28P6 28T

Operation Range Commercial 0° to 70°C

Industrial -40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C
32J 28P6 28T

Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 28-lead, Wide, Plastic Dual Inline Package PDIP 28-lead, Plastic Thin Small Outline Package TSOP
14 AT29C256

Packaging Information
32J PLCC

AT29C256

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
28P6 PDIP
More datasheets: AT29C256-12JC | AT29C256-90PC | AT29C256-12TI | AT29C256-90JI | AT29C256-70JC | AT29C256-70JI | AT29C256-70PC | AT29C256-70PI | AT29C256-70TC | AT29C256-70TI


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Datasheet ID: AT29C256-15TI 518996