AT29C1024-15JI

AT29C1024-15JI Datasheet


The AT29C1024 is a 5-volt-only in-system Flash programmable and erasable read

Part Datasheet
AT29C1024-15JI AT29C1024-15JI AT29C1024-15JI (pdf)
Related Parts Information
AT29C1024-70TI AT29C1024-70TI AT29C1024-70TI
AT29C1024-70TC AT29C1024-70TC AT29C1024-70TC
AT29C1024-70JC AT29C1024-70JC AT29C1024-70JC
AT29C1024-70JI AT29C1024-70JI AT29C1024-70JI
AT29C1024-12JI AT29C1024-12JI AT29C1024-12JI
AT29C1024-12JC AT29C1024-12JC AT29C1024-12JC
AT29C1024-12TC AT29C1024-12TC AT29C1024-12TC
AT29C1024-15JC AT29C1024-15JC AT29C1024-15JC
AT29C1024-15TC AT29C1024-15TC AT29C1024-15TC
AT29C1024-15TI AT29C1024-15TI AT29C1024-15TI
AT29C1024-90JC AT29C1024-90JC AT29C1024-90JC
AT29C1024-90JI AT29C1024-90JI AT29C1024-90JI
AT29C1024-90TC AT29C1024-90TC AT29C1024-90TC
AT29C1024-90TI AT29C1024-90TI AT29C1024-90TI
AT29C1024-12TI AT29C1024-12TI AT29C1024-12TI
PDF Datasheet Preview
• Fast Read Access Time - 70 ns
• 5-Volt Only Reprogramming
• Sector Program Operation

Single Cycle Reprogram Erase and Program 512 Sectors 128 words/sector Internal Address and Data Latches for 128 Words
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Sector Program Cycle Time - 10 ms
• DATA Polling for End of Program Detection
• Low Power Dissipation 60 mA Active Current 200 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges

The AT29C1024 is a 5-volt-only in-system Flash programmable and erasable read
only memory PEROM . Its 1 megabit of memory is organized as 65,536 words by 16
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 70 ns with power dissipation of just 330 mW. When the device
is deselected, the CMOS standby current is less than 200 µA. The device endurance
is such that any sector can typically be written to in excess of 10,000 times.

Pin Configurations
continued

Pin Name A0 - A15 CE OE WE I/O0 - I/O15 NC DC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect

PLCC Top View
6 I/O13 5 I/O14 4 I/O15 3 CE 2 NC 1 NC 44 VCC 43 WE 42 NC 41 A15 40 A14

I/O12 7 I/O11 8 I/O10 9

I/O9 10 I/O8 11 GND 12 NC 13 I/O7 14 I/O6 15 I/O5 16 I/O4 17
39 A13 38 A12 37 A11 36 A10 35 A9 34 GND 33 NC 32 A8 31 A7 30 A6 29 A5

NC 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 NC 8 A6 9 A7 10 A8 11 VSS 12 A9 13 A10 14 A11 15 NC 16 A12 17 A13 18 A14 19 A15 20 NC 21 WE 22 VCC 23 NC 24

TSOP Top View Type 1
48 NC 47 OE 46 O0 45 O1 44 O2 43 O3 42 O4 41 NC 40 O5 39 O6 38 O7 37 VSS 36 O8 35 O9 34 O10 33 NC 32 O11 31 O12 30 O13 29 O14 28 O15 27 CE 26 NC 25 NC
1-Megabit 64K x 16 5-volt Only Flash Memory AT29C1024

I/O3 18 I/O2 19 I/O1 20 I/O0 21 OE 22 DC 23

A0 24 A1 25 A2 26 A3 27 A4 28

To allow for simple in-system reprogrammability, the AT29C1024 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C1024 is performed on a sector basis 128 words of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 words of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7 or I/O15. Once the end of a program cycle has been detected, a new access for a read or program can begin.

Block Diagram

Device Operation

READ The AT29C1024 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

DATA LOAD Data loads are used to enter the 128 words of a sector to be programmed or the software codes for data protection. A data load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

PROGRAM The device is reprogrammed on a sector basis. If a word of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any word that is not loaded during the programming of its sector will be erased to read FFH. Once the words of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data word has been loaded into the device, successive words are entered in the same manner. Each new word to be programmed must have its high to low transition on WE or CE within 150 µs of the low to high transition of WE or CE of the preceding word. If a high to low transition is not detected within 150 µs of the last low to high transition, the
load period will end and the internal programming period will start. A7 to A15 specify the sector address. The sector address must be valid during each high to low transition of WE or CE . A0 to A6 specify the word address within the sector. The words may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.

SOFTWARE DATA PROTECTION A software controlled data protection feature is available on the AT29C1024. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. Once set, software data protection will remain active unless the disable command sequence is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

AT29C1024

AT29C1024

After setting SDP, any attempt to write to the device without the 3-word command sequence will start the internal write timers. No data will be written to the device however, for the duration of tWC, a read operation will effectively be a polling operation.

After the software data protection’s 3-word command code is given, a sector of data is loaded into the device using the sector programming timing specifications.

HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT29C1024 in the following ways a VCC is below 3.8V typical , the program function is inhibited b VCC power on VCC has reached the VCC sense level, the device will automatically time out 5 ms typical before programming c Program any one of OE low, CE high or WE high inhibits program cycles and d Noise of less than 15 ns typical on the WE or CE inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part i.e. using the device code , and have the system software use the appropriate sector size for program operations. In this
manner, the user can have a common board design for various Flash densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size.

For details, see Operating Modes for hardware operation or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING The AT29C1024 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7 and I/O15. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.
Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code

AT29C1024-70JC AT29C1024-70TC

AT29C1024-70JI AT29C1024-70TI

AT29C1024-90JC AT29C1024-90TC

AT29C1024-90JI AT29C1024-90TI

AT29C1024-12JC AT29C1024-12TC

AT29C1024-12JI AT29C1024-12TI

AT29C1024-15JC AT29C1024-15TC

AT29C1024-15JI AT29C1024-15TI

Package
44J 48T
44J 48T
44J 48T
44J 48T
44J 48T
44J 48T
44J 48T
44J 48T

Operation Range

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C
44J 48T

Package Type 44-Lead, Plastic J-Leaded Chip Carrier PLCC 48-Lead, Thin Small Outline Package TSOP

AT29C1024

AT29C1024

Packaging Information
44J, 44-Lead, Plastic J-Leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

JEDEC STANDARD MS-018 AA

X 45° PIN NO. 1 IDENTIFY

X 30° - 45°
.685 17.4 SQ

REF SQ

X 45° MAX 3X
48T, 48-Lead, Plastic Thin Small Outline Package TSOP Dimensions in Millimeters and Inches *

JEDEC OUTLINE MO-142 DD
More datasheets: 173P12 | PC-24-50 | AT29C1024-70TI | AT29C1024-70TC | AT29C1024-70JC | AT29C1024-70JI | AT29C1024-12JI | AT29C1024-12JC | AT29C1024-12TC | AT29C1024-15JC


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Datasheet ID: AT29C1024-15JI 518994