AT29C040A-10TI

AT29C040A-10TI Datasheet

The AT29C040A is a 5-volt-only in-system Flash Programmable and Erasable Read Only Memory PEROM . Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, the device offers access times up to 100 ns, and a low 220 mW power dissipation. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. The programming algorithm is compatible with other devices in Atmel’s 5-volt-only Flash family.

Part	Datasheet
AT29C040A-10TI	AT29C040A-10TI (pdf)

Related Parts	Information
AT29C040A-10PC	AT29C040A-10PC
AT29C040A-10PI	AT29C040A-10PI
AT29C040A-10TC	AT29C040A-10TC

PDF Datasheet Preview
Fast Read Access Time - 100 ns • 5-Volt-Only Reprogramming • Sector Program Operation Single Cycle Reprogram Erase and Program 2048 Sectors 256 bytes/sector Internal Address and Data Latches for 256-Bytes Internal Program Control and Timer • Hardware and Software Data Protection • Two 16 KB Boot Blocks with Lockout • Fast Sector Program Cycle Time - 10 ms • DATA Polling for End of Program Detection • Low Power Dissipation 40 mA Active Current 100 µA CMOS Standby Current Typical Endurance > 10,000 Cycles • Single 5V ± 10% Supply • CMOS and TTL Compatible Inputs and Outputs The AT29C040A is a 5-volt-only in-system Flash Programmable and Erasable Read Only Memory PEROM . Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, the device offers access times up to 100 ns, and a low 220 mW power dissipation. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. The programming algorithm is compatible with other devices in Atmel’s 5-volt-only Flash family. continued 4-Megabit 512K x 8 5-volt Only 256-Byte Sector CMOS Flash Memory AT29C040A Pin Configurations Pin Name Function A0 - A18 Addresses Chip Enable Output Enable Write Enable I/O0 - I/O7 Data Inputs/Outputs No Connect AT29C040A DIP Top View TSOP Top View Type 1 Description Continued To allow for simple in-system reprogrammability, the AT29C040A does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C040A is performed on a sector basis 256-bytes of data are loaded into the device and then simultaneously programmed. Block Diagram During a reprogram cycle, the address locations and 256bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin. Device Operation READ The AT29C040A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention. BYTE LOAD Byte loads are used to enter the 256bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. PROGRAM The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be erased to read FFH. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE or CE within 150 µs of the low to high transition of WE or CE of the preceding byte. If a high to low transition is not detected within 150 µs of the last low to high transition, the load period will end and the internal programming period will start. A8 to A18 specify the sector address. The sector address must be valid during each high to low tran- AT29C040A sition of WE or CE . A0 to A7 specify the byte address within the sector. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation. SOFTWARE DATA PROTECTION A software controlled data protection feature is available on the AT29C040A. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. The SDP feature protects all sectors, not just a single sector. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions. After setting SDP, any attempt to write to the device with- out the three-byte command sequence will start the inter- nal write timers. No data will be written to the device how- ever, for the duration of tWC, a read operation will effec- tively be a polling operation. continued AT29C040A Device Operation Continued After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 256-bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. Ordering Information tACC ns ICC mA Active Standby Ordering Code AT29C040A-10PC AT29C040A-10TC AT29C040A-10PI AT29C040A-10TI AT29C040A-12PC AT29C040A-12TC AT29C040A-12PI AT29C040A-12TI AT29C040A-15PC AT29C040A-15TC AT29C040A-15PI AT29C040A Package 32P6 32T 32P6 32T 32P6 32T 32P6 32T 32P6 32P6 Operation Range Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C 32P6 32T Package Type 32 Lead, Wide, Plastic Dual Inline Package PDIP 32 Lead, Thin Small Outline Package TSOP

PDF Datasheet Preview

Fast Read Access Time - 100 ns
• 5-Volt-Only Reprogramming
• Sector Program Operation

Single Cycle Reprogram Erase and Program 2048 Sectors 256 bytes/sector Internal Address and Data Latches for 256-Bytes Internal Program Control and Timer
• Hardware and Software Data Protection
• Two 16 KB Boot Blocks with Lockout
• Fast Sector Program Cycle Time - 10 ms
• DATA Polling for End of Program Detection
• Low Power Dissipation
40 mA Active Current 100 µA CMOS Standby Current Typical Endurance > 10,000 Cycles
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs

The AT29C040A is a 5-volt-only in-system Flash Programmable and Erasable Read Only Memory PEROM . Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, the device offers access times up to 100 ns, and a low 220 mW power dissipation. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. The programming algorithm is compatible with other devices in Atmel’s 5-volt-only Flash family.
continued
4-Megabit 512K x 8 5-volt Only 256-Byte Sector CMOS Flash Memory

AT29C040A

Pin Configurations

Pin Name Function

A0 - A18 Addresses

Chip Enable

Output Enable

Write Enable

I/O0 - I/O7 Data Inputs/Outputs

No Connect

AT29C040A DIP Top View

TSOP Top View

Type 1

Description Continued

To allow for simple in-system reprogrammability, the AT29C040A does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C040A is performed on a sector basis 256-bytes of data are loaded into the device and then simultaneously programmed.

Block Diagram

During a reprogram cycle, the address locations and 256bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.

Device Operation

READ The AT29C040A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention.

BYTE LOAD Byte loads are used to enter the 256bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

PROGRAM The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be erased to read FFH. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE or CE within 150 µs of the low to high transition of WE or CE of the preceding byte. If a high to low transition is not detected within 150 µs of the last low to high transition, the load period will end and the internal programming period will start. A8 to A18 specify the sector address. The sector address must be valid during each high to low tran-

AT29C040A
sition of WE or CE . A0 to A7 specify the byte address within the sector. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.

SOFTWARE DATA PROTECTION A software controlled data protection feature is available on the AT29C040A. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. The SDP feature protects all sectors, not just a single sector. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

After setting SDP, any attempt to write to the device with-
out the three-byte command sequence will start the inter-
nal write timers. No data will be written to the device how-
ever, for the duration of tWC, a read operation will effec-
tively be a polling operation.
continued

AT29C040A

Device Operation Continued

After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 256-bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation.
Ordering Information
tACC ns

ICC mA

Active Standby
Ordering Code

AT29C040A-10PC AT29C040A-10TC AT29C040A-10PI AT29C040A-10TI AT29C040A-12PC AT29C040A-12TC AT29C040A-12PI AT29C040A-12TI AT29C040A-15PC AT29C040A-15TC AT29C040A-15PI

AT29C040A

Package
32P6 32T 32P6 32T 32P6 32T 32P6 32T 32P6
32P6

Operation Range

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C
32P6 32T

Package Type 32 Lead, Wide, Plastic Dual Inline Package PDIP 32 Lead, Thin Small Outline Package TSOP

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Datasheet ID: AT29C040A-10TI 518993