AT29C040A-90JI

AT29C040A-90JI Datasheet


The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read Only Memory PEROM . Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, the device offers access times up to 90 ns, and a low 220 mW power dissipation. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. The programming algorithm is compatible with other devices in Atmel’s 5-volt only Flash family.

Part Datasheet
AT29C040A-90JI AT29C040A-90JI AT29C040A-90JI (pdf)
Related Parts Information
AT29C040A-12TC AT29C040A-12TC AT29C040A-12TC
AT29C040A-12PC AT29C040A-12PC AT29C040A-12PC
AT29C040A-12PI AT29C040A-12PI AT29C040A-12PI
AT29C040A-12JC AT29C040A-12JC AT29C040A-12JC
AT29C040A-90TI AT29C040A-90TI AT29C040A-90TI
AT29C040A-90PC AT29C040A-90PC AT29C040A-90PC
AT29C040A-90JC AT29C040A-90JC AT29C040A-90JC
AT29C040A-15JI AT29C040A-15JI AT29C040A-15JI
AT29C040A-12JI AT29C040A-12JI AT29C040A-12JI
AT29C040A-15JC AT29C040A-15JC AT29C040A-15JC
AT29C040A-90PI AT29C040A-90PI AT29C040A-90PI
AT29C040A-15PC AT29C040A-15PC AT29C040A-15PC
AT29C040A-15TI AT29C040A-15TI AT29C040A-15TI
AT29C040A-15TC AT29C040A-15TC AT29C040A-15TC
AT29C040A-15PI AT29C040A-15PI AT29C040A-15PI
AT29C040A-12TI AT29C040A-12TI AT29C040A-12TI
AT29C040A-90TC AT29C040A-90TC AT29C040A-90TC
PDF Datasheet Preview
• Fast Read Access Time 90 ns
• 5-volt Only Reprogramming
• Sector Program Operation

Single Cycle Reprogram Erase and Program 2048 Sectors 256 Bytes/Sector Internal Address and Data Latches for 256 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Two 16K Bytes Boot Blocks with Lockout
• Fast Sector Program Cycle Time 10 ms
• DATA Polling for End of Program Detection
• Low Power Dissipation 40 mA Active Current 100 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs

The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read Only Memory PEROM . Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology, the device offers access times up to 90 ns, and a low 220 mW power dissipation. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. The programming algorithm is compatible with other devices in Atmel’s 5-volt only Flash family.
4-megabit 512K x 8 5-volt Only 256-byte Sector Flash Memory

AT29C040A

Pin Configurations

Pin Name A0 - A18 CE OE WE I/O0 - I/O7 NC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect DIP Top View

A18 1 A16 2 A15 3 A12 4

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16
32 VCC 31 WE 30 A17 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3

PLCC Top View
4 A12 3 A15 2 A16 1 A18 32 VCC 31 WE 30 A17

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20

TSOP Top View Type 1

A11 1 A9 2 A8 3

A13 4 A14 5 A17 6 WE 7 VCC 8 A18 9 A16 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3

Block Diagram

To allow for simple in-system reprogrammability, the AT29C040A does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C040A is performed on a sector basis 256 bytes of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin.

Device Operation

READ The AT29C040A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

BYTE LOAD Byte loads are used to enter the 256 bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

PROGRAM The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be erased to read FFH. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE or CE within 150 µs of the low to high transition of WE or CE of the preceding byte. If a high to low transition is not detected within 150 µs of the last low to high transition, the load period will end and the internal programming period will start. A8 to A18 specify the sector address. The sector address must be valid during each high to low transition of WE or CE . A0 to A7 specify the byte address within the sector. The bytes may be loaded in any order sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.
2 AT29C040A

AT29C040A

SOFTWARE DATA PROTECTION A software controlled data protection feature is available on the AT29C040A. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector program timing specifications. The SDP feature protects all sectors, not just a single sector. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

After setting SDP, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device however, for the duration of tWC, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low respectively and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 256 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation.

HARDWARE DATA PROTECTION Hardware features protect against inadvertent programs to the AT29C040A in the following ways a VCC sense if VCC is below 3.8V typical , the program function is inhibited b VCC power on delay once VCC has reached the VCC sense level, the device will automatically time out 5 ms typical before programming c Program inhibit holding any one of OE low, CE high or WE high inhibits program cycles and d Noise filter pulses of less than 15 ns typical on the WE or CE inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part i.e. using the device code , and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size.

For details, see Operating Modes for hardware operation or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING The AT29C040A features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.

TOGGLE BIT In addition to DATA polling the AT29C040A provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.

BOOT BLOCK PROGRAMMING LOCKOUT The AT29C040A has two designated memory blocks that have a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. Each of these blocks consists of 16K bytes the programming lockout feature can be set independently for either block. While the lockout feature does not have to be activated, it can be activated for either or both blocks.

These two 16K memory sections are referred to as boot blocks. Secure code which will bring up a system can be contained in a boot block. The AT29C040A blocks are located in the first 16K bytes of memory and the last 16K bytes of memory. The boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. Once the programming lockout feature has been activated, the data in that block can no longer be erased or programmed data in other memory locations can still be changed through the regular programming methods. To activate the lockout feature, a series of seven program commands to specific addresses with specific data must be performed. Please see Boot Block Lockout Feature Enable Algorithm.
Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code

AT29C040A-90JC AT29C040A-90PC AT29C040A-90TC

AT29C040A-90JI AT29C040A-90PI AT29C040A-90TI

AT29C040A-12JC AT29C040A-12PC AT29C040A-12TC AT29C040A-12JI AT29C040A-12PI AT29C040A-12TI AT29C040A-15JC AT29C040A-15PC AT29C040A-15TC AT29C040A-15JI AT29C040A-15PI AT29C040A-15TI

AT29C040A-20JC AT29C040A-20PC AT29C040A-20TC

AT29C040A-20JI AT29C040A-20PI AT29C040A-20TI

Note:

Not recommended for New Designs.

AT29C040A

Package
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T
32J 32P6 32T
32J 32P6 32T

Operation Range Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C
32J 32P6 32T

Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 32-lead, Wide, Plastic Dual Inline Package PDIP 32-lead, Thin Small Outline Package TSOP

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
14 AT29C040A
More datasheets: CNY173300 | CNY172300 | CNY171300 | MOC81023SDL | AT29C040A-12TC | AT29C040A-12PC | AT29C040A-12PI | AT29C040A-12JC | AT29C040A-90TI | AT29C040A-90PC


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Datasheet ID: AT29C040A-90JI 518991