AT28LV64B-20JI

AT28LV64B-20JI Datasheet

The AT28LV64B is a high-performance electrically erasable programmable read only memory EEPROM . Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA.

Part	Datasheet
AT28LV64B-20JI	AT28LV64B-20JI (pdf)

Related Parts	Information
AT28LV64B-25TC	AT28LV64B-25TC
AT28LV64B-20SC	AT28LV64B-20SC
AT28LV64B-20TI	AT28LV64B-20TI
AT28LV64B-25JC	AT28LV64B-25JC
AT28LV64B-25JI	AT28LV64B-25JI
AT28LV64B-25PC	AT28LV64B-25PC
AT28LV64B-25PI	AT28LV64B-25PI
AT28LV64B-25SC	AT28LV64B-25SC
AT28LV64B-25TI	AT28LV64B-25TI
AT28LV64B-25SI	AT28LV64B-25SI

PDF Datasheet Preview
• Single 3.3V ± 10% Supply • Hardware and Software Data Protection • Low-power Dissipation 15 mA Active Current 20 µA CMOS Standby Current • Fast Read Access Time - 200 ns • Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer • Fast Write Cycle Times Page Write Cycle Time 10 ms Maximum 1 to 64 Byte Page Write Operation • DATA Polling for End of Write Detection • High-reliability CMOS Technology Endurance 100,000 Cycles Data Retention 10 Years • JEDEC Approved Byte-wide Pinout • Commercial and Industrial Temperature Ranges The AT28LV64B is a high-performance electrically erasable programmable read only memory EEPROM . Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA. continued Pin Configurations Pin Name Function PDIP, SOIC Top View A0 - A12 CE OE WE I/O0 - I/O7 NC DC Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14 28 VCC 27 WE 26 NC 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 PLCC Top View TSOP Top View 4 A7 3 A12 2 NC 1 DC 32 VCC 31 WE 30 NC A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6 I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20 Note PLCC package pins 1 and 17 are DON’T CONNECT. OE 1 A11 2 A9 3 A8 4 NC 5 WE 6 VCC 7 NC 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14 28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2 64K 8K x 8 Low-voltage Parallel EEPROM with Page Write and Software Data Protection AT28LV64B 3-Volt, 64K E2PROM with Data Protection The AT28LV64B is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 64 byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s AT28LV64B has additional features to ensure high quality and manufacturability. A software data protection mechanism guards against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. Block Diagram Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C Storage Temperature -65°C to +150°C All Input Voltages including NC Pins with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability AT28LV64B AT28LV64B Device Operation READ The AT28LV64B is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems. BYTE WRITE A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. Ordering Information 1 tACC ICC mA Active Standby Ordering Code AT28LV64B-20JC AT28LV64B-20PC AT28LV64B-20SC AT28LV64B-20TC AT28LV64B-20JI AT28LV64B-20PI AT28LV64B-20SI AT28LV64B-20TI AT28LV64B-25JC AT28LV64B-25PC AT28LV64B-25SC AT28LV64B-25TC AT28LV64B-25JI AT28LV64B-25PI AT28LV64B-25SI AT28LV64B-25TI Note See Valid Part Number table below. Package 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28LV64B JC, JI, PC, PI, SC, SI, TC, TI AT28LV64B JC, JI, PC, PI, SC, SI, TC, TI Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C 32J 28P6 28S 28T Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 28-pin, Wide, Plastic Dual Inline Package PDIP 28-lead, Wide, Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP AT28LV64B AT28LV64B Packaging Information

PDF Datasheet Preview

• Single 3.3V ± 10% Supply
• Hardware and Software Data Protection
• Low-power Dissipation
15 mA Active Current 20 µA CMOS Standby Current
• Fast Read Access Time - 200 ns
• Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer
• Fast Write Cycle Times Page Write Cycle Time 10 ms Maximum 1 to 64 Byte Page Write Operation
• DATA Polling for End of Write Detection
• High-reliability CMOS Technology Endurance 100,000 Cycles Data Retention 10 Years
• JEDEC Approved Byte-wide Pinout
• Commercial and Industrial Temperature Ranges

The AT28LV64B is a high-performance electrically erasable programmable read only memory EEPROM . Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA.
continued

Pin Configurations

Pin Name Function

PDIP, SOIC Top View

A0 - A12 CE OE WE I/O0 - I/O7 NC DC

Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect

NC 1 A12 2

A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC 27 WE 26 NC 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3

PLCC Top View

TSOP Top View
4 A7 3 A12 2 NC 1 DC 32 VCC 31 WE 30 NC

A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13
29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6

I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20

Note PLCC package pins 1 and 17 are DON’T CONNECT.

OE 1 A11 2

A9 3 A8 4 NC 5 WE 6 VCC 7 NC 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14
28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2
64K 8K x 8 Low-voltage Parallel EEPROM with Page Write and Software Data Protection AT28LV64B
3-Volt, 64K E2PROM with Data Protection

The AT28LV64B is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 64 byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of

I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.

Atmel’s AT28LV64B has additional features to ensure high quality and manufacturability. A software data protection mechanism guards against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature -65°C to +150°C

All Input Voltages including NC Pins with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

AT28LV64B

AT28LV64B

Device Operation

READ The AT28LV64B is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems.

BYTE WRITE A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.
Ordering Information 1
tACC

ICC mA

Active

Standby
Ordering Code

AT28LV64B-20JC

AT28LV64B-20PC

AT28LV64B-20SC

AT28LV64B-20TC

AT28LV64B-20JI

AT28LV64B-20PI

AT28LV64B-20SI

AT28LV64B-20TI

AT28LV64B-25JC

AT28LV64B-25PC

AT28LV64B-25SC

AT28LV64B-25TC

AT28LV64B-25JI

AT28LV64B-25PI

AT28LV64B-25SI

AT28LV64B-25TI

Note See Valid Part Number table below.

Package
32J 28P6 28S 28T
32J 28P6 28S 28T
32J 28P6 28S 28T
32J 28P6 28S 28T

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers

Speed

Package and Temperature Combinations

AT28LV64B

JC, JI, PC, PI, SC, SI, TC, TI

AT28LV64B

JC, JI, PC, PI, SC, SI, TC, TI

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C
32J 28P6 28S 28T

Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 28-pin, Wide, Plastic Dual Inline Package PDIP 28-lead, Wide, Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP

AT28LV64B

AT28LV64B

Packaging Information

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Datasheet ID: AT28LV64B-20JI 518980