AT28LV010-25TC

AT28LV010-25TC Datasheet

The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Programmable Read-Only Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA.

Part	Datasheet
AT28LV010-25TC	AT28LV010-25TC (pdf)

Related Parts	Information
AT28LV010-20TA	AT28LV010-20TA
AT28LV010-25SI	AT28LV010-25SI

PDF Datasheet Preview
• Single 3.3V ± 10% Supply • Fast Read Access Time 200 ns • Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer • Fast Write Cycle Time Page Write Cycle Time 10 ms Maximum 1 to 128-Byte Page Write Operation • Low Power Dissipation 15 mA Active Current 20 µA CMOS Standby Current • Hardware and Software Data Protection • DATA Polling for End of Write Detection • High Reliability CMOS Technology Endurance 100,000K Cycles Data Retention 10 Years • JEDEC Approved Byte-Wide Pinout • Commercial, Industrial and Automotive Temperature Ranges • Green Pb/Halide-free Packaging Option The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Programmable Read-Only Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA. The AT28LV010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s 28LV010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. Software data protection is implemented to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking. 1-Megabit 128K x 8 Low Voltage Paged Parallel EEPROMs AT28LV010 Pin Configurations Pin Name A0 - A16 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect AT28LV010 I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20 32-lead PLCC Top View 4 A12 3 A15 2 A16 1 DC 32 VCC 31 WE 30 NC A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 32-lead TSOP Top View A11 1 A9 2 A8 3 A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 A16 10 A15 11 A12 12 A7 13 A6 14 A5 15 A4 16 32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3 32-lead PDIP Top View NC 1 A16 2 A15 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16 32 VCC 31 WE 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 Block Diagram AT28LV010 Device Operation Read The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. Write The write operation of the AT28LV010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. Each write operation must be preceded by the software data protection SDP command sequence. This sequence is a series of three unique write command operations that enable the internal write circuitry. The command sequence and the data to be written must conform to the software protected write cycle timing. Addresses are latched on the falling edge of WE or CE, whichever occurs last and data is latched on the rising edge of WE or CE, whichever occurs first. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded the AT28LV010 will cease accepting data and commence the internal programming operation. If more than one data byte is to be written during a single programming operation, they must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur. DATA Polling The AT28LV010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. Toggle Bit In addition to DATA Polling the AT28LV010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. Data Protection If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. Hardware Protection Hardware features protect against inadvertent writes to the AT28LV010 in the following ways a VCC power-on delay once VCC has reached 2.0V typical the device will automatically time out 5 ms typical before allowing a write b write inhibit holding any one of OE low, CE high or WE high inhibits write cycles and c noise filter pulses of less than 15 ns typical on the WE or CE inputs will not initiate a write cycle. Ordering Information 1 Standard Package tACC ICC mA Active Standby Ordering Code AT28LV010-20JC AT28LV010-20PC AT28LV010-20TC AT28LV010-20JI AT28LV010-20PI AT28LV010-20TI AT28LV010-20TA Note See “Valid Part Numbers” below. AT28LV010-25JC AT28LV010-25PC AT28LV010-25TC AT28LV010-25JI AT28LV010-25PI AT28LV010-25TI Green Package Option Pb/Halide-free tACC ICC mA Active Standby Ordering Code AT28LV010-20JU AT28LV010-20TU 32J 32P6 32T Package Type 32-Lead, Plastic J-Leaded Chip Carrier PLCC 32-Lead, Wide, Plastic Dual Inline Package PDIP 32-Lead, Plastic Thin Small Outline Package TSOP Package 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T Package 32J 32T Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28LV010 JC, JI, JU, PC, PI, TC, TI, TU AT28LV010 JC, JI, PC, PI, TC, TI Die Products Reference Section Parallel EEPROM Die Products AT28LV010 Operation Range Commercial 0° to 70°C Industrial -40° to 85°C Automotive -40° to 125°C Commercial 0° to 70°C Industrial -40° to 85°C Operation Range Industrial -40° to 85°C Packaging Information 32J PLCC PIN NO. 1 IDENTIFIER e D1 D B1 E2 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. SYMBOL MIN NOM MAX NOTE Note 2 Note 2 10/04/01 TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131 12 AT28LV010 32P6 PDIP

PDF Datasheet Preview

• Single 3.3V ± 10% Supply
• Fast Read Access Time 200 ns
• Automatic Page Write Operation

Internal Address and Data Latches for 128 Bytes Internal Control Timer
• Fast Write Cycle Time Page Write Cycle Time 10 ms Maximum 1 to 128-Byte Page Write Operation
• Low Power Dissipation 15 mA Active Current 20 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology Endurance 100,000K Cycles Data Retention 10 Years
• JEDEC Approved Byte-Wide Pinout
• Commercial, Industrial and Automotive Temperature Ranges
• Green Pb/Halide-free Packaging Option

The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Programmable Read-Only Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA.

The AT28LV010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.

Atmel’s 28LV010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. Software data protection is implemented to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking.
1-Megabit 128K x 8 Low Voltage Paged Parallel EEPROMs

AT28LV010

Pin Configurations

Pin Name A0 - A16 CE OE WE I/O0 - I/O7 NC DC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect

AT28LV010

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20
32-lead PLCC Top View
4 A12 3 A15 2 A16 1 DC 32 VCC 31 WE 30 NC

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7
32-lead TSOP Top View

A11 1 A9 2 A8 3

A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 A16 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3
32-lead PDIP Top View

NC 1 A16 2 A15 3 A12 4

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16
32 VCC 31 WE 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3

Block Diagram

AT28LV010

Device Operation

Read

The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system.

Write

The write operation of the AT28LV010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. Each write operation must be preceded by the software data protection SDP command sequence. This sequence is a series of three unique write command operations that enable the internal write circuitry. The command sequence and the data to be written must conform to the software protected write cycle timing. Addresses are latched on the falling edge of WE or CE, whichever occurs last and data is latched on the rising edge of WE or CE, whichever occurs first. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded the AT28LV010 will cease accepting data and commence the internal programming operation. If more than one data byte is to be written during a single programming operation, they must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur.

DATA Polling

The AT28LV010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.

Toggle Bit

In addition to DATA Polling the AT28LV010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.

Hardware Protection

Hardware features protect against inadvertent writes to the AT28LV010 in the following ways a VCC power-on delay once VCC has reached 2.0V typical the device will automatically time out 5 ms typical before allowing a write b write inhibit holding any one of OE low, CE high or WE high inhibits write cycles and c noise filter pulses of less than 15 ns typical on the WE or CE inputs will not initiate a write cycle.
Ordering Information 1

Standard Package
tACC

ICC mA

Active

Standby
Ordering Code AT28LV010-20JC AT28LV010-20PC AT28LV010-20TC AT28LV010-20JI AT28LV010-20PI AT28LV010-20TI AT28LV010-20TA

Note See “Valid Part Numbers” below.

AT28LV010-25JC AT28LV010-25PC AT28LV010-25TC

AT28LV010-25JI AT28LV010-25PI AT28LV010-25TI

Green Package Option Pb/Halide-free
tACC

ICC mA

Active

Standby
Ordering Code

AT28LV010-20JU

AT28LV010-20TU
32J 32P6 32T

Package Type 32-Lead, Plastic J-Leaded Chip Carrier PLCC 32-Lead, Wide, Plastic Dual Inline Package PDIP 32-Lead, Plastic Thin Small Outline Package TSOP

Package 32J 32P6 32T 32J 32P6 32T
32J 32P6 32T 32J 32P6 32T

Package 32J 32T

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers

Speed

Package and Temperature Combinations

AT28LV010

JC, JI, JU, PC, PI, TC, TI, TU

AT28LV010

JC, JI, PC, PI, TC, TI

Die Products

Reference Section Parallel EEPROM Die Products

AT28LV010

Operation Range Commercial 0° to 70°C Industrial -40° to 85°C Automotive
-40° to 125°C Commercial 0° to 70°C Industrial -40° to 85°C

Operation Range Industrial
-40° to 85°C

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
12 AT28LV010
32P6 PDIP

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Datasheet ID: AT28LV010-25TC 518976