AT28HC256-70JC

AT28HC256-70JC Datasheet

AT28HC256

Part	Datasheet
AT28HC256-70JC	AT28HC256-70JC (pdf)

Related Parts	Information
AT28HC256F-12TI	AT28HC256F-12TI
AT28HC256F-90PI	AT28HC256F-90PI
AT28HC256F-90PC	AT28HC256F-90PC
AT28HC256-90PC	AT28HC256-90PC
AT28HC256F-90JC	AT28HC256F-90JC
AT28HC256F-12SI	AT28HC256F-12SI
AT28HC256F-12SC	AT28HC256F-12SC
AT28HC256F-12PI	AT28HC256F-12PI
AT28HC256F-12JI	AT28HC256F-12JI
AT28HC256-90PI	AT28HC256-90PI
AT28HC256F-90JI	AT28HC256F-90JI
AT28HC256-70PI	AT28HC256-70PI
AT28HC256F-12JC	AT28HC256F-12JC
AT28HC256F-70PI	AT28HC256F-70PI
AT28HC256E-70JI	AT28HC256E-70JI
AT28HC256F-70JI	AT28HC256F-70JI
AT28HC256E-90PC	AT28HC256E-90PC
AT28HC256E-70PI	AT28HC256E-70PI
AT28HC256E-90JI	AT28HC256E-90JI
AT28HC256E-12TI	AT28HC256E-12TI
AT28HC256E-12SI	AT28HC256E-12SI
AT28HC256E-12PI	AT28HC256E-12PI
AT28HC256E-12JI	AT28HC256E-12JI
AT28HC256-90JI	AT28HC256-90JI
AT28HC256-90JC	AT28HC256-90JC
AT28HC256-70JI	AT28HC256-70JI
AT28HC256E-90JC	AT28HC256E-90JC
AT28HC256E-90PI	AT28HC256E-90PI
AT28HC256-12TC	AT28HC256-12TC
AT28HC256-12JI	AT28HC256-12JI
AT28HC256-12JC	AT28HC256-12JC
AT28HC256-12PC	AT28HC256-12PC
AT28HC256-12PI	AT28HC256-12PI
AT28HC256-70PC	AT28HC256-70PC
AT28HC256-12TI	AT28HC256-12TI
AT28HC256-12SC	AT28HC256-12SC
AT28HC256-12SI	AT28HC256-12SI

PDF Datasheet Preview
• Fast Read Access Time 70 ns • Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer • Fast Write Cycle Times Page Write Cycle Time 3 ms or 10 ms Maximum 1 to 64-byte Page Write Operation • Low Power Dissipation 80 mA Active Current 3 mA Standby Current • Hardware and Software Data Protection • DATA Polling for End of Write Detection • High Reliability CMOS Technology Endurance 104 or 105 Cycles Data Retention 10 Years • Single 5V ± 10% Supply • CMOS and TTL Compatible Inputs and Outputs • JEDEC Approved Byte-wide Pinout • Full Military, Commercial, and Industrial Temperature Ranges • Green Pb/Halide-free Packaging Option 256 32K x 8 High-speed Parallel EEPROM AT28HC256 The AT28HC256 is a high-performance electrically erasable and programmable readonly memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256 is deselected, the standby current is less than 5 mA. The AT28HC256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s 28HC256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. Pin Configurations Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect 28-lead TSOP Top View OE 1 A11 2 A9 3 A8 4 A13 5 WE 6 VCC 7 A14 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14 28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2 28-lead PGA Top View 32-pad LCC, 32-lead PLCC Top View 4 A7 3 A12 2 A14 1 DC 32 VCC 31 WE 30 A13 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6 I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20 Note PLCC package pins 1 and 17 are Don’t Connect. 28-lead Cerdip/PDIP/Flatpack/SOIC Top View A14 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14 28 VCC 27 WE 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 2 AT28HC256 Block Diagram AT28HC256 Device Operation Read The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. Byte Write Page Write A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur. DATA Polling The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. Toggle Bit In addition to DATA Polling the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle. Data Protection If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. Ordering Information 1 Standard Package tACC ICC mA Active Standby Ordering Code AT28HC256 E,F -70JC AT28HC256 E,F -70PC AT28HC256 E,F -70JI AT28HC256 E,F -70PI AT28HC256 E,F -90JC AT28HC256 E,F -90PC AT28HC256 E,F -90JI AT28HC256 E,F -90PI AT28HC256 E,F -90DM/883 AT28HC256 E,F -90FM/883 AT28HC256 E,F -90LM/883 AT28HC256 E,F -90UM/883 AT28HC256 E,F -12JC AT28HC256 E,F -12PC AT28HC256 E,F -12SC AT28HC256 E,F -12TC AT28HC256 E,F -12JI AT28HC256 E,F -12PI AT28HC256 E,F -12SI AT28HC256 E,F -12TI AT28HC256 E,F -12DM/883 AT28HC256 E,F -12FM/883 AT28HC256 E,F -12LM/883 AT28HC256 E,F -12UM/883 Package 32J 28P6 32J 28P6 32J 28P6 32J 28P6 28D6 28F 32L 28U 32J 28P6 28S 28T 32J 28P6 28S 28T 28D6 28F 32L 28U 28D6 28F 32J 32L 28P6 28S 28T 28U W Blank E F Package Type 28-lead, Wide, Non-windowed, Ceramic Dual Inline Package Cerdip 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package Flatpack 32-lead, Plastic J-leaded Chip Carrier PLCC 32-pad, Non-windowed, Ceramic Leadless Chip Carrier LCC 28-lead, Wide, Plastic Dual Inline Package PDIP 28-lead, Wide Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP 28-pin, Ceramic Pin Grid Array PGA Die Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms High Endurance Option Endurance = 100K Write Cycles Fast Write Option Write Time = 3 ms AT28HC256 Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Military/883C Class B, Fully Compliant -55°C to 125°C Commercial 0°C to 70°C Industrial -40°C to 85°C Military/883C Class B, Fully Compliant -55°C to 125°C Standard Package Continued tACC ICC mA Active Standby Ordering Code 5962-88634 03 UX 5962-88634 03 XX 5962-88634 03 YX 5962-88634 03 ZX 5962-88634 04 UX 5962-88634 04 XX 5962-88634 04 YX 5962-88634 04 ZX 5962-88634 01 UX 5962-88634 01 XX 5962-88634 01 YX 5962-88634 01 ZX 5962-88634 02 UX 5962-88634 02 XX 5962-88634 02 YX 5962-88634 02 ZX Note See “Valid Part Numbers” on page Package 28U 28D6 32L 28F 28U 28D6 32L 28F 28U 28D6 32L 28F 28U 28D6 32L 28F Operation Range Military/883C Class B, Fully Compliant -55°C to 125°C Military/883C Class B, Fully Compliant -55°C to 125°C Military/883C Class B, Fully Compliant -55°C to 125°C Military/883C Class B, Fully Compliant -55°C to 125°C 28D6 28F 32J 32L 28P6 28S 28T 28U W Blank E F Package Type 28-lead, Wide, Non-windowed, Ceramic Dual Inline Package Cerdip 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package Flatpack 32-lead, Plastic J-leaded Chip Carrier PLCC 32-pad, Non-windowed, Ceramic Leadless Chip Carrier LCC 28-lead, Wide, Plastic Dual Inline Package PDIP 28-lead, Wide Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP 28-pin, Ceramic Pin Grid Array PGA Die Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms High Endurance Option Endurance = 100K Write Cycles Fast Write Option Write Time = 3 ms 14 AT28HC256 Green Package Option Pb/Halide-free tACC ICC mA Active Standby Ordering Code AT28HC256 F -90JU AT28HC256 F -90SU AT28HC256 F -90TU Package 32J 28S 28T AT28HC256 Operation Range Industrial -40°C to 85°C 32J 28S 28T Blank F Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 28-lead, Wide, Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms Fast Write Option Write Time = 3 ms Ordering Information Note Previous datasheets included the low power suffixes L, LE and LF on the At28HC256 for 120 ns and 90 ns speeds. The low power parameters are now standard therefore, the L, LE and LF suffixes are no longer required. Valid Part Numbers The following table lists standard Atmel products that can be ordered: Device Numbers Speed Package and Temperature Combinations AT28HC256 JC, JI, PC, PI AT28HC256 JC, JI, JU, PC, PI, TC, SU, TI, TU, DM/883, FM/883, UM/883 AT28HC256E JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256F JC, JI, JU, PC, PI, TC, SU, TI, TU, DM/883, FM/883, UM/883 AT28HC256 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256E JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256F JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 Die Products Reference Section Parallel EEPROM Die Products 16 AT28HC256 Packaging Information 28D6 Cerdip AT28HC256 Dimensions in Millimeters and Inches . Controlling dimension Inches. MIL-STD 1835 D-10 Config A Glass Sealed SEATING PLANE 2.54 0.100 BSC 0.127 0.005 MIN 0º~ 15º REF MAX TITLE 2325 Orchard Parkway 28D6, 28-lead, Wide, Non-windowed, R San Jose, CA 95131 Ceramic Dual Inline Package Cerdip 10/23/03 28D6 28F Flatpack Dimensions in Millimeters and Inches . Controlling dimension Inches. MIL-STD 1835 F-12 Config B PIN #1 ID TITLE 2325 Orchard Parkway 28F, 28-lead, Non-windowed, Ceramic Bottom-brazed R San Jose, CA 95131 Flat Package FlatPack 10/21/03 18 AT28HC256

PDF Datasheet Preview

• Fast Read Access Time 70 ns
• Automatic Page Write Operation

Internal Address and Data Latches for 64 Bytes Internal Control Timer
• Fast Write Cycle Times Page Write Cycle Time 3 ms or 10 ms Maximum 1 to 64-byte Page Write Operation
• Low Power Dissipation 80 mA Active Current 3 mA Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology Endurance 104 or 105 Cycles Data Retention 10 Years
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Full Military, Commercial, and Industrial Temperature Ranges
• Green Pb/Halide-free Packaging Option
256 32K x 8 High-speed Parallel EEPROM

AT28HC256

The AT28HC256 is a high-performance electrically erasable and programmable readonly memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256 is deselected, the standby current is less than 5 mA.

The AT28HC256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.

Atmel’s 28HC256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.

Pin Configurations

Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC DC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect
28-lead TSOP Top View

OE 1 A11 2

A9 3 A8 4 A13 5 WE 6 VCC 7 A14 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14
28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2
28-lead PGA Top View
32-pad LCC, 32-lead PLCC Top View
4 A7 3 A12 2 A14 1 DC 32 VCC 31 WE 30 A13

A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13
29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6

I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20

Note PLCC package pins 1 and 17 are Don’t Connect.
28-lead Cerdip/PDIP/Flatpack/SOIC Top View

A14 1 A12 2

A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC 27 WE 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3
2 AT28HC256

Block Diagram

AT28HC256

Device Operation

Read

The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system.

Byte Write Page Write

A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition during the page write operation, A6 - A14 must be the same.

The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur.

DATA Polling

The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.

Toggle Bit

In addition to DATA Polling the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle.

Data Protection

If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.
Ordering Information 1

Standard Package
tACC

ICC mA

Active

Standby
Ordering Code

AT28HC256 E,F -70JC

AT28HC256 E,F -70PC

AT28HC256 E,F -70JI

AT28HC256 E,F -70PI

AT28HC256 E,F -90JC

AT28HC256 E,F -90PC

AT28HC256 E,F -90JI AT28HC256 E,F -90PI

AT28HC256 E,F -90DM/883

AT28HC256 E,F -90FM/883

AT28HC256 E,F -90LM/883

AT28HC256 E,F -90UM/883

AT28HC256 E,F -12JC

AT28HC256 E,F -12PC

AT28HC256 E,F -12SC

AT28HC256 E,F -12TC

AT28HC256 E,F -12JI

AT28HC256 E,F -12PI

AT28HC256 E,F -12SI

AT28HC256 E,F -12TI

AT28HC256 E,F -12DM/883

AT28HC256 E,F -12FM/883

AT28HC256 E,F -12LM/883

AT28HC256 E,F -12UM/883

Package 32J 28P6 32J 28P6 32J 28P6 32J 28P6 28D6 28F 32L 28U 32J 28P6 28S 28T 32J 28P6 28S 28T 28D6 28F 32L 28U
28D6 28F 32J 32L 28P6 28S 28T 28U W

Blank E F

Package Type 28-lead, Wide, Non-windowed, Ceramic Dual Inline Package Cerdip 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package Flatpack 32-lead, Plastic J-leaded Chip Carrier PLCC 32-pad, Non-windowed, Ceramic Leadless Chip Carrier LCC 28-lead, Wide, Plastic Dual Inline Package PDIP 28-lead, Wide Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP 28-pin, Ceramic Pin Grid Array PGA Die

Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms High Endurance Option Endurance = 100K Write Cycles Fast Write Option Write Time = 3 ms

AT28HC256

Operation Range Commercial 0°C to 70°C Industrial
-40°C to 85°C Commercial 0°C to 70°C Industrial
-40°C to 85°C Military/883C

Class B, Fully Compliant -55°C to 125°C Commercial 0°C to 70°C Industrial -40°C to 85°C Military/883C

Class B, Fully Compliant -55°C to 125°C

Standard Package Continued
tACC

ICC mA

Active

Standby
Ordering Code
5962-88634 03 UX
5962-88634 03 XX
5962-88634 03 YX
5962-88634 03 ZX
5962-88634 04 UX
5962-88634 04 XX
5962-88634 04 YX
5962-88634 04 ZX
5962-88634 01 UX
5962-88634 01 XX
5962-88634 01 YX
5962-88634 01 ZX
5962-88634 02 UX
5962-88634 02 XX
5962-88634 02 YX
5962-88634 02 ZX

Note See “Valid Part Numbers” on page

Package
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F
28U 28D6 32L 28F

Operation Range Military/883C

Class B, Fully Compliant -55°C to 125°C

Military/883C Class B, Fully Compliant
-55°C to 125°C

Military/883C Class B, Fully Compliant
-55°C to 125°C

Military/883C Class B, Fully Compliant
-55°C to 125°C
28D6 28F 32J 32L 28P6 28S 28T 28U W

Blank E F

Package Type 28-lead, Wide, Non-windowed, Ceramic Dual Inline Package Cerdip 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package Flatpack 32-lead, Plastic J-leaded Chip Carrier PLCC 32-pad, Non-windowed, Ceramic Leadless Chip Carrier LCC 28-lead, Wide, Plastic Dual Inline Package PDIP 28-lead, Wide Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP 28-pin, Ceramic Pin Grid Array PGA Die

Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms High Endurance Option Endurance = 100K Write Cycles Fast Write Option Write Time = 3 ms
14 AT28HC256

Green Package Option Pb/Halide-free
tACC

ICC mA

Active Standby
Ordering Code

AT28HC256 F -90JU

AT28HC256 F -90SU

AT28HC256 F -90TU

Package
32J 28S 28T

AT28HC256

Operation Range Industrial
-40°C to 85°C
32J 28S 28T

Blank F

Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 28-lead, Wide, Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP

Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms Fast Write Option Write Time = 3 ms
Ordering Information Note

Previous datasheets included the low power suffixes L, LE and LF on the At28HC256 for 120 ns and 90 ns speeds. The low power parameters are now standard therefore, the L, LE and LF suffixes are no longer required.

Valid Part Numbers

The following table lists standard Atmel products that can be ordered:

Device Numbers

Speed

Package and Temperature Combinations

AT28HC256

JC, JI, PC, PI

AT28HC256

JC, JI, JU, PC, PI, TC, SU, TI, TU, DM/883, FM/883, UM/883

AT28HC256E

JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883

AT28HC256F

JC, JI, JU, PC, PI, TC, SU, TI, TU, DM/883, FM/883, UM/883

AT28HC256

JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883

AT28HC256E

JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883

AT28HC256F

JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883

Die Products

Reference Section Parallel EEPROM Die Products
16 AT28HC256

Packaging Information
28D6 Cerdip

AT28HC256

Dimensions in Millimeters and Inches . Controlling dimension Inches. MIL-STD 1835 D-10 Config A Glass Sealed

SEATING PLANE
2.54 0.100 BSC
0.127 0.005 MIN
0º~ 15º REF MAX

TITLE 2325 Orchard Parkway 28D6, 28-lead, Wide, Non-windowed, R San Jose, CA 95131 Ceramic Dual Inline Package Cerdip
10/23/03
28D6
28F Flatpack

Dimensions in Millimeters and Inches . Controlling dimension Inches. MIL-STD 1835 F-12 Config B

PIN #1 ID

TITLE 2325 Orchard Parkway 28F, 28-lead, Non-windowed, Ceramic Bottom-brazed R San Jose, CA 95131 Flat Package FlatPack
10/21/03
18 AT28HC256

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Datasheet ID: AT28HC256-70JC 518972