AT28C010E-12PU

AT28C010E-12PU Datasheet

AT28C010

Part	Datasheet
AT28C010E-12PU	AT28C010E-12PU (pdf)

Related Parts	Information
AT28C010E-15PU	AT28C010E-15PU
AT28C010-12PU	AT28C010-12PU
AT28C010-15PU	AT28C010-15PU

PDF Datasheet Preview
• Fast Read Access Time 120 ns • Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer • Fast Write Cycle Time Page Write Cycle Time 10 ms Maximum 1 to 128-byte Page Write Operation • Low Power Dissipation 40 mA Active Current 200 µA CMOS Standby Current • Hardware and Software Data Protection • DATA Polling for End of Write Detection • High Reliability CMOS Technology Endurance 104 or 105 Cycles Data Retention 10 Years • Single 5V ± 10% Supply • CMOS and TTL Compatible Inputs and Outputs • JEDEC Approved Byte-wide Pinout • Industrial Temperature Ranges • Green Pb/Halide-free Packaging Option 1-megabit 128K x 8 Paged Parallel EEPROM AT28C010 The AT28C010 is a high-performance electrically-erasable and programmable readonly memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 200 µA. The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s AT28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking. Pin Configurations Pin Name A0 - A16 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect 32-lead TSOP Top View A11 1 A9 2 A8 3 A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 A16 10 A15 11 A12 12 A7 13 A6 14 A5 15 A4 16 32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3 AT28C010 32-lead PDIP Top View NC 1 A16 2 A15 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16 32 VCC 31 WE 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 32-lead PLCC Top View 4 A12 3 A15 2 A16 1 DC 32 VCC 31 WE 30 NC A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20 Note PLCC package pin 1 is Don’t Connect. Block Diagram AT28C010 Device Operation Read The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. Byte Write Page Write A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. The page write operation of the AT28C010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded the AT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur. DATA Polling The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. Toggle Bit In addition to DATA Polling the AT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. Data Protection If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. has incorporated both hardware and software features that will protect the memory against inadvertent writes. Ordering Information 1 Standard Package tACC ICC mA Active Standby Ordering Code AT28C010 E -12JI AT28C010 E -12PI AT28C010 E -12TI AT28C010 E -15JI AT28C010 E -15PI AT28C010 E -15TI Note See “Valid Part Numbers” on page Green Package Option Pb/Halide-free tACC ICC mA Active Standby Ordering Code AT28C010-12JU AT28C010-12TU AT28C010 E -12JU AT28C010 E -12PU AT28C010 E -12TU AT28C010-15JU AT28C010-15TU AT28C010 E -15JU AT28C010 E -15PU AT28C010 E -15TU Package 32J 32P6 32T 32J 32P6 32T Package 32J 32T 32J 32P6 32T 32J 32T 32J 32P6 32T 32J 32P6 32T W Blank E Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 32-lead, Wide, Plastic Dual Inline Package PDIP 32-lead, Plastic Thin Small Outline Package TSOP Die Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms High-endurance Option Endurance = 100K Write Cycles Operation Range Industrial -40° to 85° C Operation Range Industrial -40° to 85° C 12 AT28C010 Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28C010 JI, JU, PI, TI, TU, PU AT28C010E JI, PI, TI, JU, PU, TU AT28C010 JI, JU, PI, TI, TU, PU AT28C010E JI, PI, TI, JU, PU, TU Die Products Reference Section Parallel EEPROM Die Products AT28C010 Packaging Information 32J PLCC PIN NO. 1 IDENTIFIER

PDF Datasheet Preview

• Fast Read Access Time 120 ns
• Automatic Page Write Operation

Internal Address and Data Latches for 128 Bytes Internal Control Timer
• Fast Write Cycle Time Page Write Cycle Time 10 ms Maximum 1 to 128-byte Page Write Operation
• Low Power Dissipation 40 mA Active Current 200 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology Endurance 104 or 105 Cycles Data Retention 10 Years
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Industrial Temperature Ranges
• Green Pb/Halide-free Packaging Option
1-megabit 128K x 8 Paged Parallel EEPROM

AT28C010

The AT28C010 is a high-performance electrically-erasable and programmable readonly memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 200 µA.

The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.

Atmel’s AT28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking.

Pin Configurations

Pin Name A0 - A16 CE OE WE I/O0 - I/O7 NC DC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect
32-lead TSOP Top View

A11 1 A9 2 A8 3

A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 A16 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3

AT28C010
32-lead PDIP Top View

NC 1 A16 2 A15 3 A12 4

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16
32 VCC 31 WE 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
32-lead PLCC Top View
4 A12 3 A15 2 A16 1 DC 32 VCC 31 WE 30 NC

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20

Note PLCC package pin 1 is Don’t Connect.

Block Diagram

AT28C010

Device Operation

Read

The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system.

Byte Write Page Write

A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

The page write operation of the AT28C010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded the AT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur.

DATA Polling

The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.

Toggle Bit

In addition to DATA Polling the AT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. has incorporated both hardware and software features that will protect the memory against inadvertent writes.
Ordering Information 1

Standard Package
tACC

ICC mA

Active Standby
Ordering Code

AT28C010 E -12JI

AT28C010 E -12PI

AT28C010 E -12TI

AT28C010 E -15JI

AT28C010 E -15PI

AT28C010 E -15TI

Note See “Valid Part Numbers” on page

Green Package Option Pb/Halide-free
tACC

ICC mA

Active Standby
Ordering Code

AT28C010-12JU

AT28C010-12TU

AT28C010 E -12JU

AT28C010 E -12PU

AT28C010 E -12TU

AT28C010-15JU

AT28C010-15TU

AT28C010 E -15JU

AT28C010 E -15PU

AT28C010 E -15TU

Package 32J 32P6 32T 32J 32P6 32T

Package 32J 32T 32J 32P6 32T 32J 32T 32J 32P6 32T
32J 32P6 32T W

Blank E

Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 32-lead, Wide, Plastic Dual Inline Package PDIP 32-lead, Plastic Thin Small Outline Package TSOP Die

Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms High-endurance Option Endurance = 100K Write Cycles

Operation Range Industrial
-40° to 85° C

Operation Range

Industrial -40° to 85° C
12 AT28C010

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers

Speed

Package and Temperature Combinations

AT28C010

JI, JU, PI, TI, TU, PU

AT28C010E

JI, PI, TI, JU, PU, TU

AT28C010

JI, JU, PI, TI, TU, PU

AT28C010E

JI, PI, TI, JU, PU, TU

Die Products

Reference Section Parallel EEPROM Die Products

AT28C010

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER

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Datasheet ID: AT28C010E-12PU 518966