AT28BV256-20SC

AT28BV256-20SC Datasheet

The AT28BV256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 200 µA.

Part	Datasheet
AT28BV256-20SC	AT28BV256-20SC (pdf)

Related Parts	Information
AT28BV256-20TC	AT28BV256-20TC
AT28BV256-20JC	AT28BV256-20JC
AT28BV256-20JI	AT28BV256-20JI
AT28BV256-20PC	AT28BV256-20PC
AT28BV256-20PI	AT28BV256-20PI
AT28BV256-20SI	AT28BV256-20SI
AT28BV256-20TI	AT28BV256-20TI

PDF Datasheet Preview
• Single 2.7V - 3.6V Supply • Fast Read Access Time 200 ns • Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer • Fast Write Cycle Times Page Write Cycle Time 10 ms Maximum 1- to 64-byte Page Write Operation • Low Power Dissipation 15 mA Active Current 20 µA CMOS Standby Current • Hardware and Software Data Protection • DATA Polling for End of Write Detection • High Reliability CMOS Technology Endurance 10,000 Cycles Data Retention 10 Years • JEDEC Approved Byte-wide Pinout • Commercial and Industrial Temperature Ranges The AT28BV256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 200 µA. 256K 32K x 8 Battery-Voltage Parallel EEPROMs AT28BV256 Pin Configurations Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect PLCC Top View 4 A7 3 A12 2 A14 1 DC 32 VCC 31 WE 30 A13 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6 PDIP, SOIC Top View A14 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14 28 VCC 27 WE 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 Note: Note PLCC package pins 1 and 17 are DON’T CONNECT. TSOP Top View OE 1 A11 2 A9 3 A8 4 A13 5 WE 6 VCC 7 A14 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14 28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2 I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20 Block Diagram The AT28BV256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s AT28BV256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. Absolute Maximum Ratings* Temperature under Bias -55°C to +125°C Storage Temperature -65°C to +150°C All Input Voltages including NC Pins with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2 AT28BV256 Device Operation AT28BV256 READ The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded the AT28BV256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur. Ordering Information 1 tACC ICC mA Active Standby Ordering Code AT28BV256-20JC AT28BV256-20PC AT28BV256-20SC AT28BV256-20TC AT28BV256-20JI AT28BV256-20PI AT28BV256-20SI AT28BV256-20TI AT28BV256-20TU AT28BV256-20JU AT28BV256-25JC AT28BV256-25PC AT28BV256-20SC AT28BV256-25TC AT28BV256-25JI AT28BV256-25PI AT28BV256-20SI AT28BV256-25TI Note See Valid Part Numbers table below. Package 32J 28P6 28S 28T 32J 28P6 28S 28T 32J Green 28T Green 32J 28P6 28S 28T 32J 28P6 28S 28T Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28BV256 JC, JI, PC, PI, SC, SI, TC, TI, TU, JU AT28BV256 JC, JI, PC, PI, SC, SI, TC, TI Die Products Reference Section Parallel EEPROM Die Products AT28BV256 Operation Range Commercial 0° to 70°C Industrial -40° to 85°C Industrial -40° to 85°C Commercial 0° to 70°C

PDF Datasheet Preview

• Single 2.7V - 3.6V Supply
• Fast Read Access Time 200 ns
• Automatic Page Write Operation

Internal Address and Data Latches for 64 Bytes Internal Control Timer
• Fast Write Cycle Times Page Write Cycle Time 10 ms Maximum 1- to 64-byte Page Write Operation
• Low Power Dissipation 15 mA Active Current 20 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology Endurance 10,000 Cycles Data Retention 10 Years
• JEDEC Approved Byte-wide Pinout
• Commercial and Industrial Temperature Ranges

The AT28BV256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 200 µA.
256K 32K x 8 Battery-Voltage Parallel EEPROMs

AT28BV256

Pin Configurations

Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC DC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect

PLCC Top View
4 A7 3 A12 2 A14 1 DC 32 VCC 31 WE 30 A13

A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13
29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6

PDIP, SOIC Top View

A14 1 A12 2

A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC 27 WE 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3

Note:

Note PLCC package pins 1 and 17 are DON’T CONNECT.

TSOP Top View

OE 1 A11 2

A9 3 A8 4 A13 5 WE 6 VCC 7 A14 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14
28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2

I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20

Block Diagram

The AT28BV256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.

Atmel’s AT28BV256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.

Absolute Maximum Ratings*

Temperature under Bias -55°C to +125°C

Storage Temperature -65°C to +150°C

All Input Voltages including NC Pins with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
2 AT28BV256

Device Operation

AT28BV256

READ The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system.

BYTE WRITE A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

PAGE WRITE The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded the AT28BV256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same.

The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur.
Ordering Information 1
tACC

ICC mA

Active

Standby
Ordering Code

AT28BV256-20JC

AT28BV256-20PC

AT28BV256-20SC

AT28BV256-20TC

AT28BV256-20JI

AT28BV256-20PI

AT28BV256-20SI

AT28BV256-20TI

AT28BV256-20TU

AT28BV256-20JU

AT28BV256-25JC

AT28BV256-25PC

AT28BV256-20SC

AT28BV256-25TC

AT28BV256-25JI

AT28BV256-25PI

AT28BV256-20SI

AT28BV256-25TI

Note See Valid Part Numbers table below.

Package
32J 28P6 28S 28T
32J 28P6 28S 28T
32J Green 28T Green
32J 28P6 28S 28T
32J 28P6 28S 28T

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers

Speed

Package and Temperature Combinations

AT28BV256

JC, JI, PC, PI, SC, SI, TC, TI, TU, JU

AT28BV256

JC, JI, PC, PI, SC, SI, TC, TI

Die Products

Reference Section Parallel EEPROM Die Products

AT28BV256

Operation Range Commercial 0° to 70°C

Industrial -40° to 85°C

Industrial -40° to 85°C Commercial 0° to 70°C

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Datasheet ID: AT28BV256-20SC 518961