AT25FS040N-SH27-T

AT25FS040N-SH27-T Datasheet

AT25FS040

Part	Datasheet
AT25FS040N-SH27-T	AT25FS040N-SH27-T (pdf)

Related Parts	Information
AT25FS040N-SH27-B	AT25FS040N-SH27-B
AT25FS040Y7-YH27-T	AT25FS040Y7-YH27-T

PDF Datasheet Preview
• Serial Peripheral Interface SPI Compatible • Supports SPI Modes 0,0 and 3 1,1 Datasheet describes Mode 0 Operation • 50 MHz Clock Rate • Byte Mode and Page Mode Program 1 to 256 Bytes Operations • Sector/Block/Page Architecture Sixteen 256 byte Pages per Sector Sixteen 4 Kbyte Sectors per Block Eight uniform 64 Kbyte Blocks • Self-timed Sector, Block and Chip Erase • Product Identification Mode with JEDEC Standard • Low-voltage Operation 2.7V VCC = 2.7V to 3.6V • Hardware and Software Write Protection Device protection with Write Protect WP Pin Write Enable and Write Disable Instructions Software Write Protection: • Upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or Entire Array • Flexible Op Codes for Maximum Compatibility • Self-timed Program Cycle 30 µs/Byte Typical • Single Cycle Reprogramming Erase and Program for Status Register • High Reliability Endurance 10,000 Write Cycles Typical • 8-lead JEDEC 150mil SOIC and 8-lead Ultra Thin Small Array Package SAP • Die Sales Waffer Form, Tape and Reel, and Bumped Wafers High Speed Small Sectored SPI Flash Memory 4M 524,288 x 8 AT25FS040 The AT25FS040 provides 4,194,304 bits of serial reprogrammable Flash memory organized as 524,288 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25FS040 is available in a space-saving 8-lead JEDEC SOIC and 8-lead Ultra Thin SAP packages. Table Pin Configuration Pin Name Function 8-lead JEDEC SOIC CS SCK SI Chip Select Serial Data Clock Serial Data Input CS 1 SO 2 WP 3 GND 4 8 VCC 7 HOLD 6 SCK 5 SI SO GND VCC WP HOLD Serial Data Output Ground Power Supply Write Protect Suspends Serial Input 8-lead SAP __V_C_C_ 8 HOLD 7 SCK 6 2 _S_O_ 4 GND Bottom View The AT25FS040 is enabled through the Chip Select pin CS and accessed via a 3-wire interface consisting of Serial Data Input SI , Serial Data Output SO , and Serial Clock SCK . All write cycles are completely self-timed. BLOCK WRITE protection for upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or the entire memory array is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Absolute Maximum Ratings* Operating to +85°C Storage Temperature to +150°C Voltage on Any Pin with Respect to Ground to +5.0V Maximum Operating Voltage 4.2V DC Output mA NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure Block Diagram 524,288 x 8 2 AT25FS040 AT25FS040 Table Pin Capacitance 1 Applicable over recommended operating range from TA = 25°C, f = MHz, VCC = +3.6V unless otherwise noted Symbol Test Conditions Ordering Information Ordering Code AT25FS040N-SH27-B 1 AT25FS040N-SH27-T 2 AT25FS040Y7-YH27-T 2 Volltage Package 8S1 8Y7 Notes “-B” denotes bulk. “-T” denotes tape and reel, SOIC = 4K per reel and SAP = 3K per reel. Operation Range Lead-Free/Halogen-Free/ NiPdAu Lead Finish Industrial Temperature to 85°C Package Type 8S1 8-lead, Wide, Plastic Gull Wing Small outline JEDEC SOIC 8Y7 8-lead, mm x mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package SAP Options Low Voltage 2.7V to 3.6V 20 AT25FS040 AT25FS040 Part Marking Scheme 8-SOIC TOP MARK Seal Year \| Seal Week \|\|\| \|---\|---\|---\|---\|---\|---\|---\|---\| ATMLHYWW \|---\|---\|---\|---\|---\|---\|---\|---\| \|---\|---\|---\|---\|---\|---\|---\|---\| Lot Number \|---\|---\|---\|---\|---\|---\|---\|---\| \| Pin 1 Indicator Dot Y = SEAL YEAR 6 2006 0 2010 7 2007 8 2008 9 2009 1 2011 2 2012 3 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 : ::: : ::: : 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-Ultra Thin SAP TOP MARK Seal Year \| Seal Week \|---\|---\|---\|---\|---\|---\|---\|---\| ATMLHYWW \|---\|---\|---\|---\|---\|---\|---\|---\| \|---\|---\|---\|---\|---\|---\|---\|---\| Lot Number \|---\|---\|---\|---\|---\|---\|---\|---\| Pin 1 Indicator Dot Y = SEAL YEAR 6 2006 0 2010 7 2007 1 2011 8 2008 2 2012 9 2009 3 2013

PDF Datasheet Preview

• Serial Peripheral Interface SPI Compatible
• Supports SPI Modes 0,0 and 3 1,1

Datasheet describes Mode 0 Operation
• 50 MHz Clock Rate
• Byte Mode and Page Mode Program 1 to 256 Bytes Operations
• Sector/Block/Page Architecture

Sixteen 256 byte Pages per Sector Sixteen 4 Kbyte Sectors per Block Eight uniform 64 Kbyte Blocks
• Self-timed Sector, Block and Chip Erase
• Product Identification Mode with JEDEC Standard
• Low-voltage Operation 2.7V VCC = 2.7V to 3.6V
• Hardware and Software Write Protection Device protection with Write Protect WP Pin Write Enable and Write Disable Instructions Software Write Protection:
• Upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or Entire Array
• Flexible Op Codes for Maximum Compatibility
• Self-timed Program Cycle
30 µs/Byte Typical
• Single Cycle Reprogramming Erase and Program for Status Register
• High Reliability

Endurance 10,000 Write Cycles Typical
• 8-lead JEDEC 150mil SOIC and 8-lead Ultra Thin Small Array Package SAP
• Die Sales Waffer Form, Tape and Reel, and Bumped Wafers

High Speed Small Sectored SPI Flash Memory
4M 524,288 x 8

AT25FS040

The AT25FS040 provides 4,194,304 bits of serial reprogrammable Flash memory organized as 524,288 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25FS040 is available in a space-saving 8-lead JEDEC SOIC and 8-lead Ultra Thin SAP packages.

Table Pin Configuration

Pin Name

Function
8-lead JEDEC SOIC

CS SCK SI

Chip Select Serial Data Clock Serial Data Input

CS 1 SO 2 WP 3 GND 4
8 VCC 7 HOLD 6 SCK 5 SI

SO GND VCC WP

HOLD

Serial Data Output Ground Power Supply Write Protect Suspends Serial Input
8-lead SAP
__V_C_C_ 8

HOLD 7

SCK 6
2 _S_O_
4 GND

Bottom View

The AT25FS040 is enabled through the Chip Select pin CS and accessed via a 3-wire interface consisting of Serial Data Input SI , Serial Data Output SO , and Serial Clock SCK . All write cycles are completely self-timed.

BLOCK WRITE protection for upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or the entire memory array is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.

Absolute Maximum Ratings*

Operating to +85°C Storage Temperature to +150°C Voltage on Any Pin with Respect to Ground to +5.0V Maximum Operating Voltage 4.2V DC Output mA
*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure Block Diagram
524,288 x 8
2 AT25FS040

AT25FS040

Table Pin Capacitance 1

Applicable over recommended operating range from TA = 25°C, f = MHz, VCC = +3.6V unless otherwise noted

Symbol Test Conditions
Ordering Information
Ordering Code AT25FS040N-SH27-B 1 AT25FS040N-SH27-T 2

AT25FS040Y7-YH27-T 2

Volltage

Package 8S1 8Y7

Notes “-B” denotes bulk. “-T” denotes tape and reel, SOIC = 4K per reel and SAP = 3K per reel.

Operation Range

Lead-Free/Halogen-Free/ NiPdAu Lead Finish

Industrial Temperature to 85°C

Package Type 8S1 8-lead, Wide, Plastic Gull Wing Small outline JEDEC SOIC 8Y7 8-lead, mm x mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package SAP

Options Low Voltage 2.7V to 3.6V
20 AT25FS040

AT25FS040

Part Marking Scheme
8-SOIC

TOP MARK

Seal Year | Seal Week
||| |---|---|---|---|---|---|---|---|

ATMLHYWW
|---|---|---|---|---|---|---|---|
|---|---|---|---|---|---|---|---| * Lot Number
|---|---|---|---|---|---|---|---| |

Pin 1 Indicator Dot

Y = SEAL YEAR 6 2006 0 2010
7 2007 8 2008 9 2009
1 2011 2 2012 3 2013

WW = SEAL WEEK 02 = Week 2 04 = Week 4 : ::: : ::: : 50 = Week 50 52 = Week 52

Lot Number to Use ALL Characters in Marking

BOTTOM MARK

No Bottom Mark
8-Ultra Thin SAP

TOP MARK

Seal Year
| Seal Week
|---|---|---|---|---|---|---|---|

ATMLHYWW
|---|---|---|---|---|---|---|---|
|---|---|---|---|---|---|---|---|

Lot Number
|---|---|---|---|---|---|---|---|

Pin 1 Indicator Dot

Y = SEAL YEAR 6 2006 0 2010 7 2007 1 2011 8 2008 2 2012 9 2009 3 2013

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT25FS040N-SH27-T Datasheet file may be downloaded here without warranties.

Datasheet ID: AT25FS040N-SH27-T 518916