AT25DF321-SU

AT25DF321-SU Datasheet

AT25DF321

Part	Datasheet
AT25DF321-SU	AT25DF321-SU (pdf)

Related Parts	Information
AT25DF321-S3U	AT25DF321-S3U

PDF Datasheet Preview
• Single 2.7V - 3.6V Supply • Serial Peripheral Interface SPI Compatible Supports SPI Modes 0 and 3 • 70 MHz Maximum Clock Frequency • Flexible, Uniform Erase Architecture 4-Kbyte Blocks 32-Kbyte Blocks 64-Kbyte Blocks Full Chip Erase • Individual Sector Protection with Global Protect/Unprotect Feature Sixty-Four 64-Kbyte Physical Sectors • Hardware Controlled Locking of Protected Sectors • Flexible Programming Byte/Page Program 1 to 256 Bytes • Automatic Checking and Reporting of Erase/Program Failures • JEDEC Standard Manufacturer and Device ID Read Methodology • Low Power Dissipation 7 mA Active Read Current Typical 15 µA Deep Power-Down Current Typical • Endurance 100,000 Program/Erase Cycles • Data Retention 20 Years • Complies with Full Industrial Temperature Range • Industry Standard Green Pb/Halide-free/RoHS Compliant Package Options 8-lead SOIC 200-mil wide 16-lead SOIC 300-mil wide 32-megabit 2.7-volt Minimum SPI Serial Flash Memory AT25DF321 The AT25DF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF321, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF321 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The AT25DF321 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT25DF321 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. Specifically designed for use in 3-volt systems, the AT25DF321 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. 2 AT25DF321 AT25DF321 Pin Descriptions and Pinouts Table Pin Descriptions Symbol CS SCK SI SO WP HOLD VCC GND Name and Function CHIP SELECT Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode not Deep Power-Down mode , and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. SERIAL INPUT The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. SERIAL OUTPUT The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. WRITE PROTECT The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 12 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. HOLD The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on page 27 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. DEVICE POWER SUPPLY The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. GROUND The ground reference for the power supply. GND should be connected to the system ground. Asserted State Low Type Input Output Input Input Power Figure 8-SOIC Top View CS 1 SO 2 WP 3 GND 4 8 VCC 7 HOLD 6 SCK 5 SI Block Diagram Figure 16-SOIC Top View HOLD 1 VCC 2 NC 3 NC 4 NC 5 NC 6 CS 7 SO 8 16 SCK 15 SI 14 NC 13 NC 12 NC 11 NC 10 GND CONTROL AND PROTECTION LOGIC SCK SI SO INTERFACE CONTROL AND LOGIC Ordering Information Green Package Options Pb/Halide-free/RoHS Compliant fSCK MHz 70 Ordering Code AT25DF321-SU Package 8S2 AT25DF321-S3U AT25DF321 Operation Range Industrial -40°C to +85°C Package Type 8-lead, Wide, Plastic Gull Wing Small Outline Package EIAJ SOIC 16-lead, Wide, Plastic Gull Wing Small Outline Package SOIC Packaging Information 8S2 EIAJ SOIC TOP VIEW END VIEW COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE SIDE VIEW Notes This drawing is for general information only refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between to mm. TITLE Package Drawing Contact 8S2, 8-lead, Body, Plastic Small Outline Package EIAJ 34 AT25DF321 16S SOIC AT25DF321 E End View Top View Side View COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 b D E H L e C NOM MAX NOTE This drawing is for general information only refer to JEDEC Drawing MS-013, Variation AA for additional information. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed mm per side. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed mm per side. L is the length of the terminal for soldering to a substrate. 2325 Orchard Parkway R San Jose, CA 95131 TITLE 16S, 16-lead, Wide Body, Plastic Gull Wing Small Outline Package SOIC History Initial release Corrected errors in datasheet. - Changed Deep Power-Down Current typical value from 4 µa to 15 µa - Changed Deep Power-Down Current maximum value from 8 µa to 25 µa 36 AT25DF321 Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2009 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

PDF Datasheet Preview

• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface SPI Compatible

Supports SPI Modes 0 and 3
• 70 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
4-Kbyte Blocks 32-Kbyte Blocks 64-Kbyte Blocks Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature Sixty-Four 64-Kbyte Physical Sectors
• Hardware Controlled Locking of Protected Sectors
• Flexible Programming Byte/Page Program 1 to 256 Bytes
• Automatic Checking and Reporting of Erase/Program Failures
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation 7 mA Active Read Current Typical 15 µA Deep Power-Down Current Typical
• Endurance 100,000 Program/Erase Cycles
• Data Retention 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green Pb/Halide-free/RoHS Compliant Package Options 8-lead SOIC 200-mil wide 16-lead SOIC 300-mil wide
32-megabit 2.7-volt Minimum SPI Serial Flash Memory

AT25DF321

The AT25DF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF321, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.

The physical sectoring and the erase block sizes of the AT25DF321 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density.

The AT25DF321 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT25DF321 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming.

Specifically designed for use in 3-volt systems, the AT25DF321 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
2 AT25DF321

AT25DF321

Pin Descriptions and Pinouts

Table Pin Descriptions

Symbol CS SCK SI SO WP

HOLD

VCC GND

Name and Function

CHIP SELECT Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode not Deep Power-Down mode , and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.

SERIAL INPUT The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.

SERIAL OUTPUT The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.

WRITE PROTECT The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 12 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible.

HOLD The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on page 27 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible.

DEVICE POWER SUPPLY The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted.

GROUND The ground reference for the power supply. GND should be connected to the system ground.

Asserted State Low

Type Input Output Input

Input

Power

Figure 8-SOIC Top View

CS 1 SO 2 WP 3 GND 4
8 VCC 7 HOLD 6 SCK 5 SI

Block Diagram

Figure 16-SOIC Top View

HOLD 1 VCC 2 NC 3 NC 4 NC 5 NC 6 CS 7 SO 8
16 SCK 15 SI 14 NC 13 NC 12 NC 11 NC 10 GND

CONTROL AND

PROTECTION LOGIC

SCK SI SO

INTERFACE CONTROL

AND LOGIC
Ordering Information

Green Package Options Pb/Halide-free/RoHS Compliant
fSCK MHz 70
Ordering Code AT25DF321-SU

Package 8S2

AT25DF321-S3U

AT25DF321

Operation Range Industrial
-40°C to +85°C

Package Type
8-lead, Wide, Plastic Gull Wing Small Outline Package EIAJ SOIC
16-lead, Wide, Plastic Gull Wing Small Outline Package SOIC

Packaging Information
8S2 EIAJ SOIC

TOP VIEW

END VIEW

COMMON DIMENSIONS

Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

SIDE VIEW

Notes This drawing is for general information only refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between to mm.

TITLE Package Drawing Contact 8S2, 8-lead, Body, Plastic Small Outline Package EIAJ
34 AT25DF321
16S SOIC

AT25DF321

E End View

Top View

Side View

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 b D E H L e C

NOM MAX

NOTE

This drawing is for general information only refer to JEDEC Drawing MS-013, Variation AA for additional information. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not
exceed mm per side. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed mm
per side. L is the length of the terminal for soldering to a substrate.
2325 Orchard Parkway R San Jose, CA 95131

TITLE 16S, 16-lead, Wide Body, Plastic Gull

Wing Small Outline Package SOIC

History

Initial release

Corrected errors in datasheet. - Changed Deep Power-Down Current typical value from 4 µa to 15 µa - Changed Deep Power-Down Current maximum value from 8 µa to 25 µa
36 AT25DF321

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
2009 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT25DF321-SU Datasheet file may be downloaded here without warranties.

Datasheet ID: AT25DF321-SU 518904