AT25DF081-SSHN-B

AT25DF081-SSHN-B Datasheet

AT25DF081

Part	Datasheet
AT25DF081-SSHN-B	AT25DF081-SSHN-B (pdf)

PDF Datasheet Preview
• Single 1.65V - 1.95V Supply • Serial Peripheral Interface SPI Compatible Supports SPI Modes 0 and 3 • 66 MHz Maximum Clock Frequency • Flexible, Uniform Erase Architecture 4-Kbyte Blocks 32-Kbyte Blocks 64-Kbyte Blocks Full Chip Erase • Individual Sector Protection with Global Protect/Unprotect Feature Sixteen 64-Kbyte Physical Sectors • Hardware Controlled Locking of Protected Sectors • Flexible Programming Byte/Page Program 1 to 256 Bytes • Automatic Checking and Reporting of Erase/Program Failures • JEDEC Standard Manufacturer and Device ID Read Methodology • Low Power Dissipation 7 mA Active Read Current Typical 8 µA Deep Power-Down Current Typical • Endurance 100,000 Program/Erase Cycles • Data Retention 20 Years • Complies with Full Industrial Temperature Range • Industry Standard Green Pb/Halide-free/RoHS Compliant Package Options 8-lead SOIC 150-mil wide 8-contact Ultra Thin DFN 5 mm x 6 mm x mm 11-ball dBGA WLCSP 8-megabit 1.65-volt Minimum SPI Serial Flash Memory AT25DF081 Not Recommended for New Designs Use AT25DL081 The AT25DF081 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF081, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF081 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The AT25DF081 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT25DF081 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. Specifically designed for use in 1.8-volt systems, the AT25DF081 supports read, program, and erase operations with a supply voltage range of 1.65V to 1.95V. No separate voltage is required for programming and erasing. 2 AT25DF081 AT25DF081 Pin Descriptions and Pinouts Table Pin Descriptions Symbol CS SCK SI SO WP HOLD VCC GND Name and Function CHIP SELECT Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode not Deep Power-Down mode , and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. SERIAL INPUT The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. SERIAL OUTPUT The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. WRITE PROTECT The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 12 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. HOLD The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on page 27 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. DEVICE POWER SUPPLY The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. GROUND The ground reference for the power supply. GND should be connected to the system ground. Asserted State Low Type Input Output Input Input Power Figure 8-SOIC Top View CS 1 SO 2 WP 3 GND 4 8 VCC 7 HOLD 6 SCK 5 SI Figure 8-UDFN Top View CS 1 SO 2 WP 3 GND 4 8 VCC 7 HOLD 6 SCK 5 SI Figure 11-dBGA Top View Through Back of Die 1234 VCC CS HOLD SO Ordering Information Ordering Code Detail Standard Package Offerings AT 2 5DF 0 8 1 Atmel Designator Product Family AT25DF081 Shipping Carrier Option B = Bulk tubes Y = Trays T = Tape and reel Operating Voltage N = 1.65V minimum 1.65V to 1.95V Device Density 08 = 8-megabit Interface 1 = Serial Device Grade H = Green, NiPdAu lead finish, industrial temperature range to +85°C U = Green, Matte Sn or Sn alloy, industrial temperature range to +85°C Package Option SS = 8-lead, wide SOIC M = 8-contact, 5mm x 6mm UDFN U = 11-ball dBGA WLCSP Green Package Options Pb/Halide-free/RoHS Compliant Ordering Code AT25DF081-SSHN-B AT25DF081-SSHN-T AT25DF081-MHN-Y AT25DF081-MHN-T Package 8S1 8MA1 Lead Finish NiPdAu Operating Voltage 1.65V to 1.95V AT25DF081-UUN-T 11U1 2 SnAgCu Notes The shipping carrier option code is not marked on the devices. Please contact Atmel for 11-ball dBGA package outline drawing. fSCK MHz 66 Operation Range Industrial -40°C to +85°C 8S1 8MA1 11U1 Package Type 8-lead, Wide, Plastic Gull Wing Small Outline Package JEDEC SOIC 8-contact, 5 mm x 6 mm Thermally Enhanced Ultra Thin Dual Flat No Lead Package UDFN 11-ball die Ball Grid Arrray dBGA Ordering Code Detail Wafer Level Options A T 2 5 D F 0 8 1 T 1 N Atmel Designator Operating Voltage N = 1.65V minimum 1.65V to 1.95V Product Family Device Density 08 = 8-megabit Die/Wafer Backgrind Thickness 20 = 20mils 11 = 11mils Die/Wafer Carrier Option T = Tape and reel Interface 1 = Serial Wafer Level Option WD = Bare die WB = Bumped die, Pb-Free Green Package Options Pb/Halide-free/RoHS Compliant Ordering Code AT25DF081-WDT20N AT25DF081-WDT11N AT25DF081-WBT11N Package Bare Die Lead Finish n/a Bumped Die Sn-Ag Operating Voltage 1.65V to 1.95V fSCK MHz 66 Notes Die/wafer carrier option code is not marked on devices. Please contact Atmel for minimum order requirements for bare die and bumped die options. Operation Range Industrial -40°C to +85°C 34 AT25DF081 Packaging Information 8S1 JEDEC SOIC AT25DF081 TOP VIEW SIDE VIEW END VIEW COMMON DIMENSIONS Unit of Measure = mm MIN NOM MAX NOTE Note These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. R Colorado Springs, CO 80906 TITLE 8S1, 8-lead Wide Body , Plastic Gull Wing Small Outline JEDEC SOIC 3/17/05 8MA1 UDFN Pin 1 ID D SIDE VIEW y TOP VIEW Pin #1 Notch R Option B BOTTOM VIEW Option A Pin #1 Chamfer C SYMBOL A A1 b C D D2 E E2 e L y K COMMON DIMENSIONS Unit of Measure = mm MIN NOM MAX NOTE Package Drawing Contact: TITLE 8MA1, 8-pad 5 x 6 x mm Body , Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package UDFN History Initial release Changed part number ordering code to reflect NiPdAu lead finish - Changed AT25DF081-SSU-1.8 to AT25DF081-SSH-1.8 - Changed AT25DF081-MU-1.8 to AT25DF081-MH-1.8 Added lead finish details to Ordering Information table Changed description from “1.8-volt Only Serial Firmware DataFlash” to “1.65-volt Minimum SPI Serial Flash” Removed 8-ball dBGA Changed Deep Power-Down current values - Increased typical value from 4 µA to 8 µA - Increased maximum value from 8 µA to 14 µA Changed typical Chip Erase time from 6 sec to 8 sec Updated Ordering Information table and changed part numbering scheme Changed 8Y7 package to 8MA1 package Added 11-ball dBGA WLCSP Updated Ordering Information table Removed “Preliminary” status from the datasheet Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2008 Atmel Corporation. All rights reserved. logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

PDF Datasheet Preview

• Single 1.65V - 1.95V Supply
• Serial Peripheral Interface SPI Compatible

Supports SPI Modes 0 and 3
• 66 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
4-Kbyte Blocks 32-Kbyte Blocks 64-Kbyte Blocks Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature Sixteen 64-Kbyte Physical Sectors
• Hardware Controlled Locking of Protected Sectors
• Flexible Programming Byte/Page Program 1 to 256 Bytes
• Automatic Checking and Reporting of Erase/Program Failures
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation 7 mA Active Read Current Typical 8 µA Deep Power-Down Current Typical
• Endurance 100,000 Program/Erase Cycles
• Data Retention 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green Pb/Halide-free/RoHS Compliant Package Options 8-lead SOIC 150-mil wide 8-contact Ultra Thin DFN 5 mm x 6 mm x mm 11-ball dBGA WLCSP
8-megabit 1.65-volt Minimum SPI Serial Flash Memory

AT25DF081

Not Recommended for New Designs

Use AT25DL081

The AT25DF081 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF081, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.

The physical sectoring and the erase block sizes of the AT25DF081 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density.

The AT25DF081 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT25DF081 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming.

Specifically designed for use in 1.8-volt systems, the AT25DF081 supports read, program, and erase operations with a supply voltage range of 1.65V to 1.95V. No separate voltage is required for programming and erasing.
2 AT25DF081

AT25DF081

Pin Descriptions and Pinouts

Table Pin Descriptions

Symbol CS SCK SI SO WP

HOLD

VCC GND

Name and Function

CHIP SELECT Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode not Deep Power-Down mode , and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.

SERIAL INPUT The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.

SERIAL OUTPUT The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.

WRITE PROTECT The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 12 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible.

HOLD The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on page 27 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible.

DEVICE POWER SUPPLY The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted.

GROUND The ground reference for the power supply. GND should be connected to the system ground.

Asserted State Low

Type Input Output Input

Input

Power

Figure 8-SOIC Top View

CS 1 SO 2 WP 3 GND 4
8 VCC 7 HOLD 6 SCK 5 SI

Figure 8-UDFN Top View

CS 1 SO 2 WP 3 GND 4
8 VCC 7 HOLD 6 SCK 5 SI

Figure 11-dBGA Top View Through Back of Die
1234

VCC CS

HOLD SO
Ordering Information
Ordering Code Detail Standard Package Offerings AT 2 5DF 0 8 1

Atmel Designator

Product Family

AT25DF081

Shipping Carrier Option

B = Bulk tubes Y = Trays T = Tape and reel

Operating Voltage

N = 1.65V minimum 1.65V to 1.95V

Device Density
08 = 8-megabit

Interface
1 = Serial

Device Grade

H = Green, NiPdAu lead finish, industrial temperature range to +85°C

U = Green, Matte Sn or Sn alloy, industrial temperature range to +85°C

Package Option

SS = 8-lead, wide SOIC M = 8-contact, 5mm x 6mm UDFN U = 11-ball dBGA WLCSP

Green Package Options Pb/Halide-free/RoHS Compliant
Ordering Code

AT25DF081-SSHN-B AT25DF081-SSHN-T

AT25DF081-MHN-Y AT25DF081-MHN-T

Package 8S1 8MA1

Lead Finish NiPdAu

Operating Voltage 1.65V to 1.95V

AT25DF081-UUN-T
11U1 2

SnAgCu

Notes The shipping carrier option code is not marked on the devices. Please contact Atmel for 11-ball dBGA package outline drawing.
fSCK MHz 66

Operation Range

Industrial -40°C to +85°C
8S1 8MA1 11U1

Package Type 8-lead, Wide, Plastic Gull Wing Small Outline Package JEDEC SOIC 8-contact, 5 mm x 6 mm Thermally Enhanced Ultra Thin Dual Flat No Lead Package UDFN 11-ball die Ball Grid Arrray dBGA
Ordering Code Detail Wafer Level Options A T 2 5 D F 0 8 1 T 1 N

Atmel Designator

Operating Voltage

N = 1.65V minimum 1.65V to 1.95V

Product Family

Device Density
08 = 8-megabit

Die/Wafer Backgrind Thickness
20 = 20mils 11 = 11mils

Die/Wafer Carrier Option

T = Tape and reel

Interface
1 = Serial

Wafer Level Option

WD = Bare die WB = Bumped die, Pb-Free

Green Package Options Pb/Halide-free/RoHS Compliant
Ordering Code AT25DF081-WDT20N AT25DF081-WDT11N

AT25DF081-WBT11N

Package Bare Die

Lead Finish n/a

Bumped Die

Sn-Ag

Operating Voltage 1.65V to 1.95V
fSCK MHz 66

Notes Die/wafer carrier option code is not marked on devices. Please contact Atmel for minimum order requirements for bare die and bumped die options.

Operation Range

Industrial -40°C to +85°C
34 AT25DF081

Packaging Information
8S1 JEDEC SOIC

AT25DF081

TOP VIEW

SIDE VIEW

END VIEW

COMMON DIMENSIONS Unit of Measure = mm

MIN NOM MAX

NOTE

Note These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
1150 E. Cheyenne Mtn. Blvd. R Colorado Springs, CO 80906

TITLE 8S1, 8-lead Wide Body , Plastic Gull Wing

Small Outline JEDEC SOIC
3/17/05
8MA1 UDFN

Pin 1 ID D

SIDE VIEW y

TOP VIEW

Pin #1 Notch R

Option B

BOTTOM VIEW

Option A

Pin #1 Chamfer C

SYMBOL A A1 b C D D2 E E2 e L y K

COMMON DIMENSIONS Unit of Measure = mm

MIN NOM MAX

NOTE

Package Drawing Contact:

TITLE 8MA1, 8-pad 5 x 6 x mm Body , Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package UDFN
History Initial release Changed part number ordering code to reflect NiPdAu lead finish
- Changed AT25DF081-SSU-1.8 to AT25DF081-SSH-1.8 - Changed AT25DF081-MU-1.8 to AT25DF081-MH-1.8 Added lead finish details to Ordering Information table Changed description from “1.8-volt Only Serial Firmware DataFlash” to “1.65-volt Minimum SPI Serial Flash” Removed 8-ball dBGA Changed Deep Power-Down current values - Increased typical value from 4 µA to 8 µA - Increased maximum value from 8 µA to 14 µA Changed typical Chip Erase time from 6 sec to 8 sec Updated Ordering Information table and changed part numbering scheme Changed 8Y7 package to 8MA1 package Added 11-ball dBGA WLCSP Updated Ordering Information table Removed “Preliminary” status from the datasheet

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
2008 Atmel Corporation. All rights reserved. logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

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Datasheet ID: AT25DF081-SSHN-B 518902