AT24C512-10UI-2.7

AT24C512-10UI-2.7 Datasheet

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory EEPROM organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to 4 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 20-pin JEDEC SOIC, 8-pin Leadless Array LAP , and 8-ball dBGA packages. In addition, the entire family is available in 5.0V 4.5V to 5.5V , 2.7V 2.7V to 5.5V and 1.8V 1.8V to 3.6V versions.

Part	Datasheet
AT24C512-10UI-2.7	AT24C512-10UI-2.7 (pdf)

Related Parts	Information
AT24C512-10TI-2.7-T	AT24C512-10TI-2.7-T
AT24C512-10UI-1.8	AT24C512-10UI-1.8
AT24C512-10PI-1.8	AT24C512-10PI-1.8
AT24C512W1-10SI-1.8	AT24C512W1-10SI-1.8
AT24C512-10PI-2.7	AT24C512-10PI-2.7
AT24C512W1-10SI-2.7	AT24C512W1-10SI-2.7
AT24C512-10TI-2.7	AT24C512-10TI-2.7
AT24C512C1-10CI-2.7	AT24C512C1-10CI-2.7
AT24C512C1-10CI-1.8	AT24C512C1-10CI-1.8
AT24C512C1-10CC-2.7	AT24C512C1-10CC-2.7
AT24C512-10TI-1.8	AT24C512-10TI-1.8

PDF Datasheet Preview
• Low-voltage and Standard-voltage Operation VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VCC = 1.8V to 3.6V • Internally Organized 65,536 x 8 • 2-wire Serial Interface • Schmitt Triggers, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz 5V , 400 kHz 2.7V and 100 kHz 1.8V Compatibility • Write Protect Pin for Hardware and Software Data Protection • 128-byte Page Write Mode Partial Page Writes Allowed • Self-timed Write Cycle 5 ms Typical • High Reliability Endurance 100,000 Write Cycles Data Retention 40 Years ESD Protection >4000V • Automotive Grade and Extended Temperature Devices Available • 8-pin PDIP and 20-pin JEDEC SOIC, 8-pin LAP, and 8-ball dBGATM Packages The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory EEPROM organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to 4 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 20-pin JEDEC SOIC, 8-pin Leadless Array LAP , and 8-ball dBGA packages. In addition, the entire family is available in 5.0V 4.5V to 5.5V , 2.7V 2.7V to 5.5V and 1.8V 1.8V to 3.6V versions. Pin Configurations Pin Name A0 - A1 SDA SCL WP NC Function Address Inputs Serial Data Serial Clock Input Write Protect No Connect 20-pin SOIC A0 1 A1 2 NC 3 NC 4 NC 5 NC 6 NC 7 NC 8 NC 9 GND 10 20 VCC 19 WP 18 NC 17 NC 16 NC 15 NC 14 NC 13 NC 12 SCL 11 SDA 8-pin PDIP A0 1 A1 2 NC 3 GND 4 8 VCC 7 WP 6 SCL 5 SDA 8-pin Leadless Array VCC 8 WP 7 SCL 6 SDA 5 1 A0 2 A1 3 NC 4 GND Bottom View 8-ball dBGA VCC 8 WP 7 SCL 6 SDA 5 1 A0 2 A1 3 NC 4 GND Bottom View 2-wire Serial EEPROM 512K 65,536 x 8 AT24C512 Absolute Maximum Ratings* Operating -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground to +7.0V Maximum Operating Voltage 6.25V DC Output mA Block Diagram NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Description SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA SDA The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES A1, A0 The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with AT24C128/256. When the pins are hardwired, as many as four 512K devices may be addressed on a single bus system device addressing is discussed in detail under the Device Addressing section . When the pins are not hardwired, the default A1 and A0 are zero. WRITE PROTECT WP The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write protect function. Memory Organization AT24C512, 512K SERIAL EEPROM The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address. AT24C512 AT24C512 Pin Capacitance 1 Ordering Information tWR max ms ICC max µA 3000 ISB max µA fMAX kHz 1000 3000 1000 1500 1500 Ordering Code AT24C512C1-10CC AT24C512-10PC AT24C512-10UC AT24C512W1-10SC AT24C512C1-10CI AT24C512-10PI AT24C512-10UI AT24C512W1-10SI AT24C512C1-10CC-2.7 AT24C512-10PC-2.7 AT24C512-10UC-2.7 AT24C512W1-10SC-2.7 AT24C512C1-10CI-2.7 AT24C512-10PI-2.7 AT24C512-10UI-2.7 AT24C512W1-10SI-2.7 AT24C512C1-10CC-1.8 AT24C512-10PC-1.8 AT24C512-10UC-1.8 AT24C512W1-10SC-1.8 AT24C512C1-10CI-1.8 AT24C512-10PI-1.8 AT24C512-10UI-1.8 AT24C512W1-10SI-1.8 Package 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C 8C1 8P3 8U3 20S Blank Package Type 8-lead, Wide, Leadless Array Package LAP 8-lead, Wide, Plastic Dual In-line Package PDIP 8-ball, die Ball Grid Array Package dBGA 20-lead, Wide, Plastic Gull Wing Small Outline JEDEC SOIC Options Standard Operation 4.5V to 5.5V Low-voltage 2.7V to 5.5V Low-voltage 1.8V to 3.6V AT24C512 Packaging Information 8C1, 8-lead, Wide, Leadless Array Package LAP Dimensions in Millimeters and Inches TOP VIEW SIDE VIEW BOTTOM VIEW * Controlling dimension millimeters 8U3, 8-ball, die Ball Grid Array Package dBGA Dimensions in Millimeters and Inches * TOP VIEW BOTTOM VIEW SIDE VIEW * Controlling dimension millimeters AT24C512 8P3, 8-lead, Wide, Plastic Dual In-line Package PDIP Dimensions in Inches and Millimeters JEDEC STANDARD MS-001 BA PIN 1 SEATING PLANE

PDF Datasheet Preview

• Low-voltage and Standard-voltage Operation

VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VCC = 1.8V to 3.6V
• Internally Organized 65,536 x 8
• 2-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz 5V , 400 kHz 2.7V and 100 kHz 1.8V Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode Partial Page Writes Allowed
• Self-timed Write Cycle 5 ms Typical
• High Reliability

Endurance 100,000 Write Cycles

Data Retention 40 Years

ESD Protection >4000V
• Automotive Grade and Extended Temperature Devices Available
• 8-pin PDIP and 20-pin JEDEC SOIC, 8-pin LAP, and 8-ball dBGATM Packages

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory EEPROM organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to 4 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 20-pin JEDEC SOIC, 8-pin Leadless Array LAP , and 8-ball dBGA packages. In addition, the entire family is available in 5.0V 4.5V to 5.5V , 2.7V 2.7V to 5.5V and 1.8V 1.8V to 3.6V versions.

Pin Configurations

Pin Name A0 - A1 SDA SCL WP NC

Function Address Inputs Serial Data Serial Clock Input Write Protect No Connect
20-pin SOIC

A0 1 A1 2 NC 3 NC 4 NC 5 NC 6 NC 7 NC 8 NC 9 GND 10
20 VCC 19 WP 18 NC 17 NC 16 NC 15 NC 14 NC 13 NC 12 SCL 11 SDA
8-pin PDIP

A0 1 A1 2 NC 3 GND 4
8 VCC 7 WP 6 SCL 5 SDA
8-pin Leadless Array

VCC 8 WP 7 SCL 6 SDA 5
1 A0 2 A1 3 NC 4 GND

Bottom View
8-ball dBGA

VCC 8 WP 7 SCL 6 SDA 5
1 A0 2 A1 3 NC 4 GND

Bottom View
2-wire Serial EEPROM
512K 65,536 x 8

AT24C512

Absolute Maximum Ratings*

Operating -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground to +7.0V Maximum Operating Voltage 6.25V DC Output mA

Block Diagram
*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Pin Description

SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.

SERIAL DATA SDA The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.

DEVICE/PAGE ADDRESSES A1, A0 The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with AT24C128/256. When the pins are hardwired, as many as four 512K devices may be addressed on a single bus system device addressing is discussed in detail under the Device Addressing section . When the pins are not hardwired, the default A1 and A0 are zero.

WRITE PROTECT WP The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write protect function.

Memory Organization

AT24C512, 512K SERIAL EEPROM The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address.

AT24C512

AT24C512

Pin Capacitance 1
Ordering Information
tWR max ms

ICC max µA
3000

ISB max µA
fMAX kHz
1000
3000
1000
1500
1500
Ordering Code

AT24C512C1-10CC AT24C512-10PC AT24C512-10UC AT24C512W1-10SC

AT24C512C1-10CI AT24C512-10PI AT24C512-10UI AT24C512W1-10SI

AT24C512C1-10CC-2.7 AT24C512-10PC-2.7 AT24C512-10UC-2.7 AT24C512W1-10SC-2.7

AT24C512C1-10CI-2.7 AT24C512-10PI-2.7 AT24C512-10UI-2.7 AT24C512W1-10SI-2.7

AT24C512C1-10CC-1.8 AT24C512-10PC-1.8 AT24C512-10UC-1.8 AT24C512W1-10SC-1.8

AT24C512C1-10CI-1.8 AT24C512-10PI-1.8 AT24C512-10UI-1.8 AT24C512W1-10SI-1.8

Package
8C1 8P3 8U3 20S
8C1 8P3 8U3 20S
8C1 8P3 8U3 20S
8C1 8P3 8U3 20S
8C1 8P3 8U3 20S
8C1 8P3 8U3 20S

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C
8C1 8P3 8U3 20S

Blank

Package Type 8-lead, Wide, Leadless Array Package LAP 8-lead, Wide, Plastic Dual In-line Package PDIP 8-ball, die Ball Grid Array Package dBGA 20-lead, Wide, Plastic Gull Wing Small Outline JEDEC SOIC

Options Standard Operation 4.5V to 5.5V Low-voltage 2.7V to 5.5V Low-voltage 1.8V to 3.6V

AT24C512

Packaging Information
8C1, 8-lead, Wide, Leadless Array Package LAP Dimensions in Millimeters and Inches *

TOP VIEW

SIDE VIEW

BOTTOM VIEW
* Controlling dimension millimeters
8U3, 8-ball, die Ball Grid Array Package dBGA Dimensions in Millimeters and Inches *

TOP VIEW

BOTTOM VIEW

SIDE VIEW
* Controlling dimension millimeters

AT24C512
8P3, 8-lead, Wide, Plastic Dual In-line Package PDIP Dimensions in Inches and Millimeters

JEDEC STANDARD MS-001 BA

PIN 1

SEATING PLANE

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT24C512-10UI-2.7 Datasheet file may be downloaded here without warranties.

Datasheet ID: AT24C512-10UI-2.7 518889