AT17C65-10PC

AT17C65-10PC Datasheet

The AT17C65/128/256 and AT17LV65/128/256 low-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The low-density AT17 Series is packaged in the 8-pin PDIP, 8-lead SOIC, and the popular 20-lead PLCC and SOIC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a feature of the AT17 Series, the user can select the polarity of the reset function by programming a special EEPROM byte. These devices also support a write-protection mechanism within its programming mode.

Part	Datasheet
AT17C65-10PC	AT17C65-10PC (pdf)

Related Parts	Information
AT17C256-10SC	AT17C256-10SC
AT17C128-10JI	AT17C128-10JI
AT17C128-10JC	AT17C128-10JC
AT17C128-10PC	AT17C128-10PC
AT17C256-10JC	AT17C256-10JC
AT17C256-10PC	AT17C256-10PC
AT17C65-10JC	AT17C65-10JC
AT17C128-10NC	AT17C128-10NC
AT17C128-10NI	AT17C128-10NI
AT17C256-10NC	AT17C256-10NC
AT17C256-10NI	AT17C256-10NI
AT17C65-10SI	AT17C65-10SI
AT17C65-10NI	AT17C65-10NI
AT17C65-10SC	AT17C65-10SC
AT17C128-10PI	AT17C128-10PI
AT17C128-10SC	AT17C128-10SC
AT17C128-10SI	AT17C128-10SI
AT17C65-10CC	AT17C65-10CC
AT17C256-10JI	AT17C256-10JI
AT17C256-10PI	AT17C256-10PI
AT17C256-10SI	AT17C256-10SI
AT17C128-10CC	AT17C128-10CC
AT17C65-10JI	AT17C65-10JI
AT17C65-10PI	AT17C65-10PI
AT17C65-10NC	AT17C65-10NC

PDF Datasheet Preview
• EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • In-System Programmable via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT6000, AT40K FPGAs, Altera Devices, Lucent FPGAs, Xilinx XC3000, XC4000, XC5200, FPGAs, Motorola MPA1000 FPGAs • Cascadable Read Back to Support Additional Configurations or Future Higher-density Arrays 128K and 256K only • Low-power CMOS EEPROM Process • Programmable Reset Polarity • Available in the Space-efficient Plastic DIP or SOIC Packages PLCC Package is Pin-compatible Across Product Family • Emulation of Atmel’s AT24CXXX Serial EEPROMs • Available in 3.3V ± 10% LV and 5V ± 5% C Versions • Low-power Standby Mode The AT17C65/128/256 and AT17LV65/128/256 low-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The low-density AT17 Series is packaged in the 8-pin PDIP, 8-lead SOIC, and the popular 20-lead PLCC and SOIC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a feature of the AT17 Series, the user can select the polarity of the reset function by programming a special EEPROM byte. These devices also support a write-protection mechanism within its programming mode. The AT17 Series Configurators can be programmed with industry-standard programmers, or Atmel’s ATDH2200E Programming Kit. FPGA Configuration EEPROM Memory 64K, 128K and 256K AT17C65 AT17LV65 AT17C128 AT17LV128 AT17C256 AT17LV256 Pin Configurations 20-lead PLCC 3 NC 2 DATA 1 NC 20 VCC 19 NC CLK 4 NC 5 WP RESET/OE 6 NC 7 CE 8 18 NC 17 SER_EN 16 NC 15 NC 14 CEO A2 20-lead SOIC NC 1 DATA 2 NC 3 CLK 4 NC 5 WP RESET/OE 6 NC 7 CE 8 NC 9 GND 10 20 VCC 19 NC 18 NC 17 SER_EN 16 NC 15 NC 14 CEO A2 13 NC 12 NC 11 NC NC 9 GND 10 NC 11 NC 12 NC 13 8-pin PDIP DATA 1 CLK 2 WP RESET/OE 3 CE 4 8 VCC 7 SER_EN 6 CEO A2 5 GND 8-lead SOIC DATA 1 CLK 2 WP RESET/OE 3 CE 4 8 VCC 7 SER_EN 6 CEO A2 5 GND Block Diagram POWER ON RESET FPGA Master Serial Mode Summary The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The AT17 Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode. This document discusses the AT6000 FPGA interface. For more details or AT40K FPGA applications, please reference “AT6000 Series Configuration” or “AT40K Series Configuration” application notes. Controlling the Low-density AT17 Series Serial EEPROMs During Configuration Most connections between the FPGA device and the AT17 Serial EEPROM are simple and self-explanatory. • The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the AT17 Series Configurator. • The CEO output of any AT17C/LV128/256 drives the CE input of the next AT17C/LV128/256 in a cascade chain of EEPROMs. An AT17C/LV65 can only be used at the end of a cascade chain or as a standalone device. • SER_EN must be connected to VCC except during ISP . There are two different ways to use the inputs CE and OE. Ordering Information 5V Devices Memory Size 64K 128K 256K Ordering Code AT17C65-10PC AT17C65-10NC AT17C65-10JC AT17C65-10SC AT17C65-10PI AT17C65-10NI AT17C65-10JI AT17C65-10SI AT17C128-10PC AT17C128-10NC AT17C128-10JC AT17C128-10SC AT17C128-10PI AT17C128-10NI AT17C128-10JI AT17C128-10SI AT17C256-10PC AT17C256-10NC AT17C256-10JC AT17C256-10SC AT17C256-10PI AT17C256-10NI AT17C256-10JI AT17C256-10SI AT17C/LV65/128/256 Package 8P3 8S1 20J 20S 8P3 8S1 20J 20S 8P3 8S1 20J 20S 8P3 8S1 20J 20S 8P3 8S1 20J 20S 8P3 8S1 20J 20S Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Package Type 8-pin, Wide, Plastic Dual Inline Package PDIP 8-lead, Wide, Plastic Gull Wing Small Outline JEDEC SOIC 20-lead, Plastic J-leaded Chip Carrier PLCC 20-lead, Wide, Plastic Gull Wing Small Outline SOIC Ordering Information 3.3V Devices Memory Size 64K 128K Ordering Code AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10SC AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV65-10SI AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI 256K AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI AT17LV256-10SI Package 8P3 8S1 20J 20S 8P3 8S1 20J 20S 8P3 8S1 20J 20S 8P3 8S1 20J 20S 8P3 8S1 20J 20S 8P3 8S1 20J 20S Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C 8P3 8S1 20J 20S Package Type 8-pin, Wide, Plastic Dual Inline Package PDIP 8-lead, Wide, Plastic Gull Wing Small Outline JEDEC SOIC 20-lead, Plastic J-leaded Chip Carrier PLCC 20-lead, Wide, Plastic Gull Wing Small Outline SOIC AT17C/LV65/12 Packaging Information 8P3, 8-pin, Wide, Plastic Dual Inline Package PDIP Dimensions in Inches and Millimeters JEDEC STANDARD MS-001 BA PIN 1 SEATING PLANE 20J, 20-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters JEDEC STANDARD MS-018 AA AT17C/LV65/128/ 8S1, 8-lead, Wide, Plastic Gull Wing Small Outline JEDEC SOIC Dimensions in Inches and Millimeters PIN 1 20S, 20-lead, Wide, Plastic Gull Wing Small Outline SOIC Dimensions in Inches and Millimeters PIN 1 0 REF 8 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 408 441-0311 FAX 408 487-2600 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL 44 1276-686-677 FAX 44 1276-686-697 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369

PDF Datasheet Preview

• EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs
• In-System Programmable via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K FPGAs, Altera Devices, Lucent

FPGAs, Xilinx XC3000, XC4000, XC5200, FPGAs, Motorola MPA1000 FPGAs
• Cascadable Read Back to Support Additional Configurations or Future Higher-density

Arrays 128K and 256K only
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in the Space-efficient Plastic DIP or SOIC Packages PLCC Package is

Pin-compatible Across Product Family
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V ± 10% LV and 5V ± 5% C Versions
• Low-power Standby Mode

The AT17C65/128/256 and AT17LV65/128/256 low-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The low-density AT17 Series is packaged in the 8-pin PDIP, 8-lead SOIC, and the popular 20-lead PLCC and SOIC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a feature of the AT17 Series, the user can select the polarity of the reset function by programming a special EEPROM byte. These devices also support a write-protection mechanism within its programming mode.

The AT17 Series Configurators can be programmed with industry-standard programmers, or Atmel’s ATDH2200E Programming Kit.

FPGA Configuration EEPROM Memory
64K, 128K and 256K

AT17C65 AT17LV65 AT17C128 AT17LV128 AT17C256 AT17LV256

Pin Configurations
20-lead PLCC
3 NC 2 DATA 1 NC 20 VCC 19 NC

CLK 4 NC 5 WP RESET/OE 6 NC 7 CE 8
18 NC 17 SER_EN 16 NC 15 NC 14 CEO A2
20-lead SOIC

NC 1 DATA 2

NC 3 CLK 4 NC 5 WP RESET/OE 6 NC 7 CE 8 NC 9 GND 10
20 VCC 19 NC 18 NC 17 SER_EN 16 NC 15 NC 14 CEO A2 13 NC 12 NC 11 NC

NC 9 GND 10

NC 11 NC 12 NC 13
8-pin PDIP

DATA 1 CLK 2

WP RESET/OE 3 CE 4
8 VCC 7 SER_EN 6 CEO A2 5 GND
8-lead SOIC

DATA 1 CLK 2

WP RESET/OE 3 CE 4
8 VCC 7 SER_EN 6 CEO A2 5 GND

Block Diagram

POWER ON RESET

FPGA Master Serial Mode Summary

The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The AT17 Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode.

This document discusses the AT6000 FPGA interface. For more details or AT40K FPGA applications, please reference “AT6000 Series Configuration” or “AT40K Series Configuration” application notes.

Controlling the Low-density AT17 Series Serial EEPROMs During Configuration

Most connections between the FPGA device and the AT17 Serial EEPROM are simple and self-explanatory.
• The DATA output of the AT17 Series Configurator drives

DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17 Series Configurator.
• The CEO output of any AT17C/LV128/256 drives the CE input of the next AT17C/LV128/256 in a cascade chain of EEPROMs. An AT17C/LV65 can only be used at the end of a cascade chain or as a standalone device.
• SER_EN must be connected to VCC except during ISP .

There are two different ways to use the inputs CE and OE.
Ordering Information 5V Devices

Memory Size 64K
128K
256K
Ordering Code

AT17C65-10PC AT17C65-10NC AT17C65-10JC AT17C65-10SC

AT17C65-10PI AT17C65-10NI AT17C65-10JI AT17C65-10SI

AT17C128-10PC AT17C128-10NC AT17C128-10JC AT17C128-10SC

AT17C128-10PI AT17C128-10NI AT17C128-10JI AT17C128-10SI

AT17C256-10PC AT17C256-10NC AT17C256-10JC AT17C256-10SC

AT17C256-10PI AT17C256-10NI AT17C256-10JI AT17C256-10SI

AT17C/LV65/128/256

Package
8P3 8S1 20J 20S
8P3 8S1 20J 20S
8P3 8S1 20J 20S
8P3 8S1 20J 20S
8P3 8S1 20J 20S
8P3 8S1 20J 20S

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C

Package Type
8-pin, Wide, Plastic Dual Inline Package PDIP
8-lead, Wide, Plastic Gull Wing Small Outline JEDEC SOIC
20-lead, Plastic J-leaded Chip Carrier PLCC
20-lead, Wide, Plastic Gull Wing Small Outline SOIC
Ordering Information 3.3V Devices

Memory Size 64K
128K
Ordering Code

AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10SC

AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV65-10SI

AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC

AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI
256K

AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC

AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI AT17LV256-10SI

Package
8P3 8S1 20J 20S
8P3 8S1 20J 20S
8P3 8S1 20J 20S
8P3 8S1 20J 20S
8P3 8S1 20J 20S
8P3 8S1 20J 20S

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C
8P3 8S1 20J 20S

Package Type 8-pin, Wide, Plastic Dual Inline Package PDIP 8-lead, Wide, Plastic Gull Wing Small Outline JEDEC SOIC 20-lead, Plastic J-leaded Chip Carrier PLCC 20-lead, Wide, Plastic Gull Wing Small Outline SOIC

AT17C/LV65/12

Packaging Information
8P3, 8-pin, Wide, Plastic Dual Inline Package PDIP Dimensions in Inches and Millimeters

JEDEC STANDARD MS-001 BA

PIN 1

SEATING PLANE
20J, 20-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

JEDEC STANDARD MS-018 AA

AT17C/LV65/128/
8S1, 8-lead, Wide, Plastic Gull Wing Small Outline JEDEC SOIC Dimensions in Inches and Millimeters

PIN 1
20S, 20-lead, Wide, Plastic Gull Wing Small Outline SOIC Dimensions in Inches and Millimeters

PIN 1
0 REF 8

Atmel Headquarters

Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 408 441-0311 FAX 408 487-2600

Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL 44 1276-686-677 FAX 44 1276-686-697

Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369

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Datasheet ID: AT17C65-10PC 518856