AT17C512-10JC
AT17C512-10JC Datasheet
The AT17C512/010 and AT17LV512/010 high-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for programming Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-lead LAP, 8-lead PDIP and the popular 20-lead PLCC. The AT17 Series uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices support a write protection mode and a system-friendly READY pin, which signifies a “good” power level to the FPGA and can be used to ensure reliable system power-up.
| Part | Datasheet |
|---|---|
AT17C512-10JC |
AT17C512-10JC (pdf) |
| Related Parts | Information |
|---|---|
AT17LV010-10CC |
AT17LV010-10CC |
|
AT17C512-10CC |
AT17C512-10CC |
|
AT17C010-10CI |
AT17C010-10CI |
AT17C512-10JI |
AT17C512-10JI |
|
AT17C512-10PC |
AT17C512-10PC |
|
AT17C512-10CI |
AT17C512-10CI |
|
AT17C010-10PI |
AT17C010-10PI |
|
AT17C512-10PI |
AT17C512-10PI |
AT17C010-10JI |
AT17C010-10JI |
|
AT17LV010-10CI |
AT17LV010-10CI |
|
AT17C010-10CC |
AT17C010-10CC |
|
AT17C010-10PC |
AT17C010-10PC |
AT17C010-10JC |
AT17C010-10JC |
| PDF Datasheet Preview |
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| • EE Programmable 524,288 x 1- and 1,048,576 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • In-System Programmable via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera APEX Devices, Lucent FPGAs, Xilinx XC3000 , XC4000 , XC5200 , Virtex FPGAs • Cascadable Read Back to Support Additional Configurations or Higher-density Arrays • Low-power CMOS EEPROM Process • Programmable Reset Polarity • Available in 6 mm x 6 mm x 1 mm 8-lead LAP Pin-compatible with 8-lead SOIC/VOIC Packages , 8-lead PDIP and 20-lead PLCC Packages Pin Compatible Across Product Family • Emulation of Atmel’s AT24CXXX Serial EEPROMs • Available in 3.3V ± 10% LV and 5V ± 5% C Versions • System-friendly READY Pin • Low-power Standby Mode The AT17C512/010 and AT17LV512/010 high-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for programming Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-lead LAP, 8-lead PDIP and the popular 20-lead PLCC. The AT17 Series uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices support a write protection mode and a system-friendly READY pin, which signifies a “good” power level to the FPGA and can be used to ensure reliable system power-up. The AT17 Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. FPGA Configuration EEPROM Memory 512-kilobit and 1-megabit AT17C512 AT17LV512 AT17C010 AT17LV010 Pin Configurations 8-lead LAP DATA 1 CLK 2 RESET/OE 3 CE 4 8 VCC 7 SER_EN 6 CEO A2 5 GND 8-lead PDIP DATA 1 CLK 2 RESET/OE 3 CE 4 8 VCC 7 SER_EN 6 CEO A2 5 GND 20-lead PLCC 3 NC 2 DATA 1 NC 20 VCC 19 NC CLK 4 WP1 5 RESET/OE 6 WP2 7 18 NC 17 SER_EN 16 NC 15 READY 14 CEO A2 NC 9 GND 10 NC 11 NC 12 NC 13 2 AT17C512/010/LV512/010 Block Diagram SER_EN WP1 WP2 OSC CONTROL POWER ON RESET PROGRAMMING MODE LOGIC ROW ADDRESS COUNTER BIT COUNTER AT17C512/010/LV512/010 PROGRAMMING DATA SHIFT REGISTER ROW DECODER EEPROM CELL MATRIX COLUMN DECODER CLK READY RESET/OE CEO A2 DATA Ordering Information 5V Devices Memory Size 512-Kbit 1-Mbit Ordering Code AT17C512-10CC AT17C512-10PC AT17C512-10JC AT17C512-10CI AT17C512-10PI AT17C512-10JI AT17C010-10CC AT17C010-10PC AT17C010-10JC AT17C010-10CI AT17C010-10PI AT17C010-10JI Ordering Information 3.3V Devices Memory Size 512-Kbit Ordering Code AT17LV512-10CC AT17LV512-10PC AT17LV512-10JC 1-Mbit AT17LV512-10CI AT17LV512-10PI AT17LV512-10JI AT17LV010-10CC AT17LV010-10PC AT17LV010-10JC AT17LV010-10CI AT17LV010-10PI AT17LV010-10JI Package 8CN4 8P3 20J 8CN4 8P3 20J 8CN4 8P3 20J 8CN4 8P3 20J Package 8CN4 8P3 20J 8CN4 8P3 20J 8CN4 8P3 20J 8CN4 8P3 20J Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C 8CN4 8P3 20J Package Type 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package LAP Pin-compatible with 8-lead SOIC/VOID Packages 8-lead, Wide, Plastic Dual Inline Package PDIP 20-lead, Plastic J-leaded Chip Carrier PLCC 14 AT17C512/010/LV512/010 Packaging Information 8CN4 LAP AT17C512/010/LV512/010 Marked Pin1 Indentifier mm TYP Top View Bottom View Note Metal Pad Dimensions. Side View Pin1 Corner COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE TITLE 1150 E.Cheyenne Mtn Blvd. 8CN4, 8-lead 6 x 6 x mm Body , Lead Pitch mm, R Colorado Springs, CO 80906 Leadless Array Package LAP 11/14/01 8CN4 8P3 PDIP D PIN 1 SEATING PLANE 4 PLACES COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOTE |
| More datasheets: AT17LV010-10CC | AT17C512-10CC | AT17C010-10CI | AT17C512-10JI | AT17C512-10PC | AT17C512-10CI | AT17C010-10PI | AT17C512-10PI | AT17C010-10JI | AT17LV010-10CI |
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