AT49LW080-33JX-T

AT49LW080-33JX-T Datasheet


AT49LW080

Part Datasheet
AT49LW080-33JX-T AT49LW080-33JX-T AT49LW080-33JX-T (pdf)
Related Parts Information
AT49LW080-33JX AT49LW080-33JX AT49LW080-33JX
AT49LW080-33JC-T AT49LW080-33JC-T AT49LW080-33JC-T
AT49LW080-33JC AT49LW080-33JC AT49LW080-33JC
AT49LW080-33TC AT49LW080-33TC AT49LW080-33TC
AT49LW080-33TC-T AT49LW080-33TC-T AT49LW080-33TC-T
PDF Datasheet Preview
• Low Pin Count LPC BIOS Device
• Functions as Firmware Hub for Intel 8XX, E7XXX and E8XXX Chipsets
• 8M Bits of Flash Memory for Platform Code/Data Storage

Uniform, 64-Kbyte Memory Sectors Automated Byte-program and Sector-erase Operations
• Two Configurable Interfaces Firmware Hub FWH Interface for In-System Operation Address/Address Multiplexed A/A Mux Interface for Programming during

Manufacturing
• Firmware Hub Hardware Interface Mode
5-signal Communication Interface Supporting x8 Reads and Writes Read and Write Protection for Each Sector Using Software-controlled Registers Two Hardware Write-protect Pins One for the Top Boot Sector, One for All Other

Sectors Five General-purpose Inputs, GPIs, for Platform Design Flexibility Operates with 33 MHz PCI Clock and 3.3V I/O
• Address/Address Multiplexed A/A Mux Interface 11-pin Multiplexed Address and 8-pin Data Interface Supports Fast On-board or Out-of-system Programming
• Power Supply Specifications VCC 3.3V ± 0.3V VPP 3.3V and 12V for Fast Programming
• Industry-standard Packages 40-lead TSOP or 32-lead PLCC
• Green Pb/Halide-free Packaging Option
8-megabit Firmware Hub Flash Memory

AT49LW080

The AT49LW080 is a Flash memory device designed to be compatible with the Intel 82802AC and the Intel 82802AB Firmware Hub FWH devices for PC-Bios Application. A feature of the AT49LW080 is the nonvolatile memory core. The highperformance memory is arranged in sixteen 64-Kbyte sectors see page

The AT49LW080 supports two hardware interfaces Firmware Hub FWH for in-system operation and Address/Address Multiplexed A/A Mux for programming during manufacturing. The IC Interface Configuration pin of the device provides the control between the interfaces. The interface mode needs to be selected prior to power-up or before return from reset RST or INIT low to high transition .

An internal Command User Interface CUI serves as the control center between the two device interfaces FWH and A/A Mux and internal operation of the nonvolatile memory. A valid command sequence written to the CUI initiates device automation.

Specifically designed for 3V systems, the AT49LW080 supports read operations at 3.3V and sector erase and program operations at 3.3V and 12V VPP. The 12V VPP option renders the fastest program performance which will increase factory throughput, but is not recommended for standard in-system FWH operation in the platform. With the 3.3V VPP option, VCC and VPP should be tied together for a simple, low-power 3V design. In addition to the voltage flexibility, the dedicated VPP pin gives complete
data protection when VPP VPPLK. Internal VPP detection circuitry automatically configures the device for sector erase and program operations. Note that, while current for 12V programming will be drawn from VPP, 3.3V programming board solutions should design such that VPP draws from the same supply as VCC, and should assume that full programming current may be drawn from either pin.

Pin Configurations
32-lead PLCC Top View
4 FGPI2 [A8] 3 FGPI3 [A9] 2 RST [RST] 1 VPP [VPP] 32 VCC [VCC] 31 CLK [R/C] 30 FGPI4 [A10]
[A7] FGPI1 5 [A6] FGPI0 6
[A5] WP 7 [A4] TBL 8 [A3] ID3 9 [A2] ID2 10 [A1] ID1 11 [A0] ID0 12 [I/O0] FWH0 13
29 IC VIL [IC VIH ] 28 GNDa [GNDa] 27 VCCa [VCCa] 26 GND [GND] 25 VCC [VCC] 24 INIT [OE] 23 FWH4 [WE] 22 RFU [RY/BY] 21 RFU [I/O7]
[I/O1] FWH1 14 [I/O2] FWH2 15 [GND] GND 16 [I/O3] FWH3 17
[I/O4] RFU 18 [I/O5] RFU 19 [I/O6] RFU 20
32-lead TSOP Top View
[ ] Designates A/A Mux Mode

NC 1 [IC VIH ] IC VIL 2
[NC] NC 3 [NC] NC 4 [NC] NC 5 [NC] NC 6 [A10] FGPI4 7 [NC] NC 8 [R/C] CLK 9 [VCC] VCC 10 [VPP] VPP 11 [RST] RST 12 [NC] NC 13 [NC] NC 14 [A9] FGPI3 15 [A8] FGPI2 16 [A7] FGPI1 17 [A6] FGPI0 18 [A5] WP 19 [A4] TBL 20
40 GNDa [GNDa] 39 VCCa [VCCa] 38 FWH4 [WE] 37 INIT [OE] 36 RFU [RY/BY] 35 RFU [I/O7] 34 RFU [I/O6] 33 RFU [I/O5] 32 RFU [I/O4] 31 VCC [VCC] 30 GND [GND] 29 GND [GND] 28 FWH3 [I/O3] 27 FWH2 [I/O2] 26 FWH1 [I/O1] 25 FWH0 [I/O0] 24 ID0 [A0] 23 ID1 [A1] 22 ID2 [A2] 21 ID3 [A3]
[ ] Designates A/A Mux Mode
2 AT49LW080

AT49LW080

Firmware Hub Interface

The Firmware Hub FWH interface is designed to work with the I/O Controller Hub ICH during platform operation.

The FWH interface consists primarily of a five-signal communication interface used to control the operation of the device in a system environment. The buffers for this interface are PCI compliant. To ensure the effective delivery of security and manageability features, the FWH interface is the only way to get access to the full feature set of the device. The FWH interface is equipped to operate at 33 MHz, synchronous with the PCI bus.

Address/Address Multiplexed Interface

The A/A Mux interface is designed as a programming interface for OEMs to use during motherboard manufacturing or component pre-programming.

The A/A Mux refers to the multiplexed row and column addresses in this interface. This approach is required so that the device can be tested and programmed quickly with automated test equipment ATE and PROM programmers in the OEM’s manufacturing flow. This interface also allows the device to have an efficient programming interface with potentially large future densities, while still fitting into a 32-pin package. Only basic reads, programming, and erase of the nonvolatile memory sectors can be performed through the A/A Mux interface. In this mode FWH features, security features and registers are unavailable. A row/column R/C pin determines which set of addresses “rows or columns” are latched.

Block Diagram

WP TBL FGPI 4:0 ID 3:0 FWH 4:0 CLK INIT

OE R/C WE RY/BY

A10 - A0

I/O7 - I/O0

FWH INTERFACE

A/A MUX INTERFACE
Ordering Information

Standard Package

ICC mA

Active

Standby
Ordering Code AT49LW080-33JC AT49LW080-33TC

Green Package Option Pb/Halide-free

ICC mA

Active

Standby
Ordering Code

AT49LW080-33JX

AT49LW080

Package 32J 40T

Operation Range Extended Commercial
0° to 85°C

Package 32J

Operation Range Extended Commercial
0° to 85°C

Package Type
32-lead, Plastic J-leaded Chip Carrier Package PLCC
40-lead, Thin Small Outline Package TSOP

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
32 AT49LW080
40T TSOP

PIN 1

AT49LW080
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation CD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC
More datasheets: M13185 SL001 | M13185 SL005 | G630HAA2621EU | G630H641621EU | G630HAA1621EU | G630H982621EU | G630H361621EU | WD1003N | 350NH3G | AT49LW080-33JX


Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT49LW080-33JX-T Datasheet file may be downloaded here without warranties.

Datasheet ID: AT49LW080-33JX-T 518712