AT49LV1024-70VC

AT49LV1024-70VC Datasheet

The AT49LV1024 and the AT49LV1025 are 3-volt only in-system Flash memories. Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with power dissipation of just 90 mW over the commercial temperature range. The only difference between the AT49LV1024 and the AT49LV1025 is the package.

Part	Datasheet
AT49LV1024-70VC	AT49LV1024-70VC (pdf)

Related Parts	Information
AT49LV1025-70JC	AT49LV1025-70JC
AT49LV1025-90JC	AT49LV1025-90JC
AT49LV1024-90VC	AT49LV1024-90VC
AT49LV1024-90VI	AT49LV1024-90VI

PDF Datasheet Preview
I/O3 18 I/O2 19 I/O1 20 I/O0 21 OE 22 NC 23 A0 24 A1 25 A2 26 A3 27 A4 28 • Single-voltage Operation 3V Read 3.1V Programming • Fast Read Access Time 55 ns • Internal Program Control and Timer • 8K Word Boot Block with Lockout • Fast Erase Cycle Time 10 seconds • Word-by-Word Programming 20 µs/Word Typical • Hardware Data Protection • Data Polling for End of Program Detection • Small 10 x 14 mm VSOP Package • Typical 10,000 Write Cycles The AT49LV1024 and the AT49LV1025 are 3-volt only in-system Flash memories. Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with power dissipation of just 90 mW over the commercial temperature range. The only difference between the AT49LV1024 and the AT49LV1025 is the package. To allow for simple in-system reprogrammability, the AT49LV1024/1025 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49LV1024/1025 is performed continued Pin Configurations Pin Name A0 - A15 CE OE WE I/O0 - I/O15 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect AT49LV1025 PLCC Top View 6 I/O13 5 I/O14 4 I/O15 3 CE 2 NC 1 NC 44 VCC 43 WE 42 NC 41 A15 40 A14 I/O12 7 I/O11 8 I/O10 9 I/O9 10 I/O8 11 GND 12 NC 13 I/O7 14 I/O6 15 I/O5 16 I/O4 17 39 A13 38 A12 37 A11 36 A10 35 A9 34 GND 33 NC 32 A8 31 A7 30 A6 29 A5 AT49LV1024 VSOP Top View Type 1 10 x 14 mm A9 1 A10 2 A11 3 A12 4 A13 5 A14 6 A15 7 NC 8 WE 9 VCC 10 NC 11 CE 12 I/O15 13 I/O14 14 I/O13 15 I/O12 16 I/O11 17 I/O10 18 I/O9 19 I/O8 20 40 GND 39 A8 38 A7 37 A6 36 A5 35 A4 34 A3 33 A2 32 A1 31 A0 30 OE 29 I/O0 28 I/O1 27 I/O2 26 I/O3 25 I/O4 24 I/O5 23 I/O6 22 I/O7 21 GND 1-megabit 64K x 16 3-volt Only Flash Memory AT49LV1024 AT49LV1025 Block Diagram by erasing a block of data entire chip or main memory block and then programming on a word by word basis. The typical word programming time is a fast 20 µs. The end of a program cycle can be optionally detected by the Data Polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K word boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed. VCC GND OE WE CE ADDRESS INPUTS OE, CE, AND WE LOGIC Y DECODER X DECODER DATA INPUTS/OUTPUTS I/O15 - I/O0 DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING MAIN MEMORY 56K WORDS OPTIONAL BOOT BLOCK 8K WORDS FFFFH 2000H 1FFFH 0000H Device Operation READ The AT49LV1024/1025 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. CHIP ERASE When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same Chip Erase command See Command Definitions table . If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode. MAIN MEMORY ERASE As an alternative to the chip erase, a main memory block erase can be performed, which will erase all words not located in the boot block region to an FFFFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six-bus cycle operation. The address 5555H is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE. The main memory erase starts after the rising edge of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The main memory erase operation is internally controlled it will automatically time to completion. AT49LV1024 Ordering Information tACC ICC mA Active Standby Ordering Code AT49LV1024-55VC AT49LV1024-70VC AT49LV1024-90VC AT49LV1024-90VI AT49LV1025 Ordering Information tACC ICC mA Active Standby Ordering Code AT49LV1025-55JC AT49LV1025-70JC AT49LV1025-90JC AT49LV1025-90JI AT49LV1024/1025 Package 40V Operation Range Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial -40° to 85°C Package 44J Operation Range Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial -40° to 85°C Package Type 40-lead, Thin Small Outline Package VSOP 10 mm x 14 mm 44-lead, Plastic, J-leaded Chip Carrier Package PLCC Packaging Information 40V, 40-lead, Plastic Thin Small Outline Package VSOP Dimensions in Millimeters and Inches * *Controlling dimension millimeters 44J, 44-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters JEDEC STANDARD MS-018 AC X 45° PIN NO. 1 IDENTIFY X 30° - 45° .656 16.7 SQ .685 17.4 SQ REF SQ X 45° MAX 3X 14 AT49LV1024/1025 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 408 441-0311 FAX 408 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL 41 26-426-5555 FAX 41 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL 81 3-3523-3551 FAX 81 3-3523-7581 Atmel Product Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 719 576-3300 FAX 719 540-1759 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL 33 4-7658-3000 FAX 33 4-7658-3480 Atmel Heilbronn Theresienstrasse 2 POB 3535 D-74025 Heilbronn, Germany TEL 49 71 31 67 25 94 FAX 49 71 31 67 24 23 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL 33 0 2 40 18 FAX 33 0 2 40 18 19 60 Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL 33 4-4253-6000 FAX 33 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL 44 1355-357-000 FAX 44 1355-242-743 Fax-on-Demand North America 1- 800 292-8635 International 1- 408 441-0732 e-mail Web Site BBS 1- 408 436-4309

PDF Datasheet Preview

I/O3 18 I/O2 19 I/O1 20 I/O0 21 OE 22 NC 23

A0 24 A1 25 A2 26 A3 27 A4 28
• Single-voltage Operation 3V Read
3.1V Programming
• Fast Read Access Time 55 ns
• Internal Program Control and Timer
• 8K Word Boot Block with Lockout
• Fast Erase Cycle Time 10 seconds
• Word-by-Word Programming 20 µs/Word Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Small 10 x 14 mm VSOP Package
• Typical 10,000 Write Cycles

The AT49LV1024 and the AT49LV1025 are 3-volt only in-system Flash memories. Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with power dissipation of just 90 mW over the commercial temperature range. The only difference between the AT49LV1024 and the AT49LV1025 is the package.

To allow for simple in-system reprogrammability, the AT49LV1024/1025 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49LV1024/1025 is performed
continued

Pin Configurations

Pin Name A0 - A15 CE OE WE I/O0 - I/O15 NC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect

AT49LV1025 PLCC Top View
6 I/O13 5 I/O14 4 I/O15 3 CE 2 NC 1 NC 44 VCC 43 WE 42 NC 41 A15 40 A14

I/O12 7 I/O11 8 I/O10 9

I/O9 10 I/O8 11 GND 12 NC 13 I/O7 14 I/O6 15 I/O5 16 I/O4 17
39 A13 38 A12 37 A11 36 A10 35 A9 34 GND 33 NC 32 A8 31 A7 30 A6 29 A5

AT49LV1024 VSOP Top View Type 1
10 x 14 mm

A9 1 A10 2 A11 3 A12 4 A13 5 A14 6 A15 7 NC 8 WE 9 VCC 10 NC 11 CE 12 I/O15 13 I/O14 14 I/O13 15 I/O12 16 I/O11 17 I/O10 18 I/O9 19 I/O8 20
40 GND 39 A8 38 A7 37 A6 36 A5 35 A4 34 A3 33 A2 32 A1 31 A0 30 OE 29 I/O0 28 I/O1 27 I/O2 26 I/O3 25 I/O4 24 I/O5 23 I/O6 22 I/O7 21 GND
1-megabit 64K x 16 3-volt Only Flash Memory AT49LV1024 AT49LV1025

Block Diagram
by erasing a block of data entire chip or main memory block and then programming on a word by word basis. The typical word programming time is a fast 20 µs. The end of a program cycle can be optionally detected by the Data Polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed.

VCC GND

OE WE CE

ADDRESS INPUTS

OE, CE, AND WE LOGIC

Y DECODER X DECODER

DATA INPUTS/OUTPUTS I/O15 - I/O0

DATA LATCH

INPUT/OUTPUT BUFFERS

Y-GATING

MAIN MEMORY 56K WORDS

OPTIONAL BOOT BLOCK 8K WORDS

FFFFH
2000H 1FFFH
0000H

Device Operation

READ The AT49LV1024/1025 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

CHIP ERASE When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same Chip Erase command See Command Definitions table . If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode.

MAIN MEMORY ERASE As an alternative to the chip erase, a main memory block erase can be performed, which will erase all words not located in the boot block region to an FFFFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six-bus cycle operation. The address 5555H is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE. The main memory erase starts after the rising edge of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The main memory erase operation is internally controlled it will automatically time to completion.
AT49LV1024 Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT49LV1024-55VC

AT49LV1024-70VC

AT49LV1024-90VC

AT49LV1024-90VI
AT49LV1025 Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT49LV1025-55JC

AT49LV1025-70JC

AT49LV1025-90JC

AT49LV1025-90JI

AT49LV1024/1025

Package 40V

Operation Range Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial -40° to 85°C

Package 44J

Operation Range Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial -40° to 85°C

Package Type
40-lead, Thin Small Outline Package VSOP 10 mm x 14 mm
44-lead, Plastic, J-leaded Chip Carrier Package PLCC

Packaging Information
40V, 40-lead, Plastic Thin Small Outline Package VSOP Dimensions in Millimeters and Inches *
*Controlling dimension millimeters
44J, 44-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

JEDEC STANDARD MS-018 AC

X 45° PIN NO. 1 IDENTIFY

X 30° - 45°
.656 16.7 SQ
.685 17.4 SQ

REF SQ

X 45° MAX 3X
14 AT49LV1024/1025

Atmel Headquarters

Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 408 441-0311 FAX 408 487-2600

Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL 41 26-426-5555 FAX 41 26-426-5500

Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369

Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL 81 3-3523-3551 FAX 81 3-3523-7581

Atmel Product Operations

Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 719 576-3300 FAX 719 540-1759

Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL 33 4-7658-3000 FAX 33 4-7658-3480

Atmel Heilbronn Theresienstrasse 2 POB 3535 D-74025 Heilbronn, Germany TEL 49 71 31 67 25 94 FAX 49 71 31 67 24 23

Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL 33 0 2 40 18 FAX 33 0 2 40 18 19 60

Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL 33 4-4253-6000 FAX 33 4-4253-6001

Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL 44 1355-357-000 FAX 44 1355-242-743

Fax-on-Demand North America 1- 800 292-8635

International 1- 408 441-0732
e-mail

Web Site

BBS 1- 408 436-4309

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Datasheet ID: AT49LV1024-70VC 518711