AT49LD3200 AT49LD3200B SFlash
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AT49LD3200B-10TC (pdf) |
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AT49LD3200B-10TI |
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AT49LD3200-20TC |
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AT49LD3200-13TI |
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AT49LD3200-13TC |
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AT49LD3200-10TI |
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AT49LD3200-10TC |
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AT49LD3200-20TI |
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AT49LD3200B-20TI |
PDF Datasheet Preview |
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• 3.0V to 3.6V Read/Write • Burst Read Performance <100 MHz RAS Latency = 2, CAS Latency = 6 , 10 ns Cycle Time tSAC = 7 ns <75 MHz RAS Latency = 2, CAS Latency = 5 , 13 ns Cycle Time tSAC = 8 ns <50 MHz RAS Latency = 1, CAS Latency = 4 , 20 ns Cycle Time tSAC = 9 ns • MRS Cycle with Address Key Programs RAS Latency 1 and 2 CAS Latency 2 ~ 8 Burst Length 4, 8 Burst Type Sequential and Interleaved • Word Selectable Organization 16 Word Mode /x 32 Double Word Mode • Sector Erase Architecture Eight 256K Word or 128K Double Word 4-Mbit Sectors • Independent Asynchronous Boot Block 8K x 16 Bits with Hardware Lockout • Fast Program Time 3-volt, 100 µs per Word/Double Word Typical 12-volt, 30 µs per Word/Double Word Typical • Fast Sector Erase Time Seconds at 3 Volts Seconds at 12 Volts • Low-power Operation ICC Read = 75 mA Typical • Input and Output Pin Continuity Test Mode Optimizes Off-board Programming • Package: 86-pin TSOP Type II with Off-center Parting Line OCPL for Improved Reliability • LVTTL-compatible Inputs and Outputs 32-megabit 1M x 32 or 2M x 16 High-speed Synchronous Flash Memory AT49LD3200 AT49LD3200B SFlash The AT49LD3200 or AT49LD3200B SFlash is a synchronous, high-bandwidth Flash memory fabricated with Atmel’s high-performance CMOS process technology and is organized either as 2,097,152 x 16 bits word mode or as 1,048,576 x 32 bits double word mode , depending on the polarity of the WORD pin see Pin Function Description Table . Synchronous design allows precise cycle control. I/O transactions are possible on every clock cycle. All operations are synchronized to the rising edge of the system clock. The range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high-bandwidth, high-performance memory system applications. The AT49LD3200B will automatically activate the Asynchronous Boot Block after power-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be activated through Mode Register Set. The synchronous DRAM interface allows designers to maximize system performance while eliminating the need to shadow slow asynchronous Flash memory into highspeed RAM. The 32-megabit SFlash device is designed to sit on the synchronous memory bus and operate alongside SDRAM. Pin Configuration To maximize system manufacturing throughput the AT49LD3200 B features highspeed 12-volt program and erase options. Additionally, stand-alone programming cycle time of individual devices or modules is optimized with Atmel’s unique input and output pin continuity test mode. VCC 1 DQ0 2 VCCQ 3 DQ16 4 DQ1 5 VSSQ 6 DQ17 7 DQ2 8 VCCQ 9 DQ18 10 DQ3 11 VSSQ 12 DQ19 13 MR 14 VCC 15 DQM 16 NC 17 CAS 18 RAS 19 CS 20 WORD 21 A12 22 A11 23 A10 24 A0 25 A1 26 A2 27 NC 28 VCC 29 NC 30 DQ4 31 VSSQ 32 DQ20 33 DQ5 34 VCCQ 35 DQ21 36 DQ6 37 VSSQ 38 DQ22 39 DQ7 40 VCCQ 41 DQ23 42 VCC 43 TSOP Type II Top View 86 VSS 85 DQ31 84 VSSQ 83 DQ15 82 DQ30 81 VCCQ 80 DQ14 79 DQ29 78 VSSQ 77 DQ13 76 DQ28 75 VCCQ 74 DQ12 73 NC 72 VSS 71 NC 70 VPP 69 WE 68 CLK 67 CKE 66 A9 65 A8 64 A7 63 A6 62 A5 61 A4 60 A3 59 NC 58 VSS 57 NC 56 DQ27 55 VCCQ 54 DQ11 53 DQ26 52 VSSQ 51 DQ10 50 DQ25 49 VCCQ 48 DQ9 47 DQ24 46 VSSQ 45 DQ8 44 VSS 2 AT49LD3200 B AT49LD3200 B Pin Function Description Pin CLK CS A0 - A12 MR DQ0 - DQ31 VCC/VSS VCCQ/VSSQ WORD DQM NC WE VPP Name System Clock Chip Select Clock Enable Address Row Address Strobe Column Address Strobe Ordering Information Max Freq MHz ICC mA Active Standby Ordering Code AT49LD3200-10TC AT49LD3200-10TI AT49LD3200-13TC AT49LD3200-13TI AT49LD3200-20TC AT49LD3200-20TI AT49LD3200 B Package 86T Operation Range Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C Package Type 86-lead, Thin Small Outline Package TSOP Type II Packaging Information 86T TSOP Type II PIN 1 Identifier PIN 1 E1 E L SEATING PLANE A L1 GAGE PLANE This package conforms to JEDEC reference MO-142, Variation EC. Dimensions D and E1 do not include mold protrusion. Allowable protrusion on E1 is mm per side and on D is mm per side. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 D E E1 L L1 b c e MIN NOM MAX BASIC BASIC NOTE Note 2 Note 2 TITLE 2325 Orchard Parkway 86T, 86-lead mm Body Width Thin Small Outline Package R San Jose, CA 95131 TSOP Type ll 10/18/01 38 AT49LD3200 B Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 USA TEL 1 408 441-0311 FAX 1 408 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL 41 26-426-5555 FAX 41 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL 852 2721-9778 FAX 852 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL 81 3-3523-3551 FAX 81 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1 408 441-0311 FAX 1 408 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1 408 441-0311 FAX 1 408 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL 33 2-40-18-18-18 FAX 33 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL 33 4-42-53-60-00 FAX 33 4-42-53-60-01 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. |
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