AT49F8192AT-70TI

AT49F8192AT-70TI Datasheet

The AT49F008A T and AT49F8192A T are 5-volt, 8-megabit Flash memories organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 90 ns with power dissipation of just 275 mW. When deselected, the CMOS standby current is less than 100 µA.

Part	Datasheet
AT49F8192AT-70TI	AT49F8192AT-70TI (pdf)

Related Parts	Information
AT49F8192A-90TI	AT49F8192A-90TI

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• Single-voltage Operation 5V Read 5V Programming • Fast Read Access Time 70 ns • Internal Erase/Program Control • Sector Architecture One 8K Word 16K Bytes Boot Block with Programming Lockout Two 4K Word 8K Bytes Parameter Blocks One 496K Word 992K Bytes Main Memory Array Block • Fast Sector Erase Time 10 seconds • Byte-by-byte or Word-by-word Programming 10 µs Typical • Hardware Data Protection • Data Polling for End of Program Detection • Low Power Dissipation 50 mA Active Current 100 µA CMOS Standby Current • Typical 10,000 Write Cycles 8-megabit 1M x 8/ 512K x 16 Flash Memory The AT49F008A T and AT49F8192A T are 5-volt, 8-megabit Flash memories organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 90 ns with power dissipation of just 275 mW. When deselected, the CMOS standby current is less than 100 µA. The device contains a user-enabled “boot block” protection feature. Two versions of the feature are available the AT49F008A/8192A locates the boot block at lowest order addresses “bottom boot” the AT49F008AT/8192AT locates it at highest order addresses “top boot” . To allow for simple in-system reprogrammability, the AT49F008A T /8192A T does not require high-input voltages for programming. Reading data out of the device is similar to reading from an EPROM it has standard CE, OE and WE inputs to avoid bus contention. Reprogramming the AT49F008A T /8192A T is performed by first erasing a block of data and then programming on a byte-by-byte or word-by-word basis. Pin Configurations Pin Name A0 - A18 CE OE WE RESET RDY/BUSY I/O0 - I/O14 I/O15 A-1 BYTE NC Function Addresses Chip Enable Output Enable Write Enable Reset Ready/Busy Output Data Inputs/Outputs I/O15 Data Input/Output, Word Mode A-1 LSB Address Input, Byte Mode Selects Byte or Word Mode No Connect AT49F008A AT49F008AT AT49F8192A AT49F8192AT AT49F8192A T TSOP Top View Type 1 A15 1 A14 2 A13 3 A12 4 A11 5 A10 6 A9 7 A8 8 NC 9 NC 10 WE 11 RESET 12 NC 13 NC 14 NC 15 A18 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24 48 A16 47 BYTE 46 GND 45 I/O15 / A-1 44 I/O7 43 I/O14 42 I/O6 41 I/O13 40 I/O5 39 I/O12 38 I/O4 37 VCC 36 I/O11 35 I/O3 34 I/O10 33 I/O2 32 I/O9 31 I/O1 30 I/O8 29 I/O0 28 OE 27 GND 26 CE 25 A0 AT49F8192A T SOIC SOP Top View NC 1 A18 2 A17 3 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 CE 12 GND 13 OE 14 I/O0 15 I/O8 16 I/O1 17 I/O9 18 I/O2 19 I/O10 20 I/O3 21 I/O11 22 44 RESET 43 WE 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BYTE 32 GND 31 I/O15 30 I/O7 29 I/O14 28 I/O6 27 I/O13 26 I/O5 25 I/O12 24 I/O4 23 VCC AT49F008A T TSOP Top View Type 1 A16 1 A15 2 A14 3 A13 4 A12 5 A11 6 A9 7 A8 8 WE 9 RESET 10 NC 11 RDY/BUSY 12 A18 13 A7 14 A6 15 A5 16 A4 17 A3 18 A2 19 A1 20 40 A17 39 GND 38 NC 37 A-1 36 A10 35 I/O7 34 I/O6 33 I/O5 32 I/O4 31 VCC 30 VCC 29 NC 28 I/O3 27 I/O2 26 I/O1 25 I/O0 24 OE 23 GND 22 CE 21 A0 Note: “•” denotes a white dot marked on the package. The device is erased by executing the Erase command sequence the device internally controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections the boot block, and the main memory array block. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K word boot block section includes a reprogramming lockout feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of volts or less are used. The boot sector is designed to contain user secure code. For the AT49F8192A T , the BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic “1” or left open, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tristated and the I/O15 pin is used as an input for the LSB A-1 address function. 2 AT49F008A T /8192A T AT49F008A T Block Diagram AT49F008A T /8192A T VCC GND OE WE CE RESET ADDRESS INPUTS CONTROL LOGIC Y DECODER X DECODER AT49F008A DATA INPUTS/OUTPUTS I/O0 - I/O7 AT49F008A Ordering Information tACC ICC mA Active Standby Ordering Code AT49F008A-70TI AT49F008A-90TI AT49F8192A T Ordering Information tACC ICC mA Active Standby Ordering Code AT49F8192A-70TI AT49F8192AT-70TI AT49F8192A-90TI AT49F8192AT-90RI AT49F8192AT-90TI Package 40T Operation Range Industrial -40° to 85°C Industrial -40° to 85°C Package 48T 44R 48T Operation Range Industrial -40° to 85°C Industrial -40° to 85°C Industrial -40° to 85°C Industrial -40° to 85°C Package Type 44-lead, Wide, Plastic Gull Wing Small Outline Package SOIC 40-lead, Plastic Thin Small Outline Package TSOP 48-lead, Plastic Thin Small Outline Package TSOP 14 AT49F008A T /8192A T Packaging Information 44R SOIC AT49F008A T /8192A T Dimensions in Millimeters and Inches . Controlling dimension Inches. PIN 1 0º ~ 8º TITLE 2325 Orchard Parkway 44R, 44-lead Body Plastic Gull Wing Small Outline SOIC R San Jose, CA 95131 04/11/01 40T TSOP PIN 1 0º ~ 8º c Pin 1 Identifier SEATING PLANE GAGE PLANE This package conforms to JEDEC reference MO-142, Variation CD. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 D D1 E L L1 b c e MIN NOM MAX BASIC

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• Single-voltage Operation 5V Read 5V Programming
• Fast Read Access Time 70 ns
• Internal Erase/Program Control
• Sector Architecture

One 8K Word 16K Bytes Boot Block with Programming Lockout Two 4K Word 8K Bytes Parameter Blocks One 496K Word 992K Bytes Main Memory Array Block
• Fast Sector Erase Time 10 seconds
• Byte-by-byte or Word-by-word Programming 10 µs Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Low Power Dissipation 50 mA Active Current 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles
8-megabit 1M x 8/ 512K x 16 Flash Memory

The AT49F008A T and AT49F8192A T are 5-volt, 8-megabit Flash memories organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 90 ns with power dissipation of just 275 mW. When deselected, the CMOS standby current is less than 100 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of the feature are available the AT49F008A/8192A locates the boot block at lowest order addresses “bottom boot” the AT49F008AT/8192AT locates it at highest order addresses “top boot” .

To allow for simple in-system reprogrammability, the AT49F008A T /8192A T does not require high-input voltages for programming. Reading data out of the device is similar to reading from an EPROM it has standard CE, OE and WE inputs to avoid bus contention. Reprogramming the AT49F008A T /8192A T is performed by first erasing a block of data and then programming on a byte-by-byte or word-by-word basis.

Pin Configurations

Pin Name A0 - A18 CE OE WE RESET RDY/BUSY I/O0 - I/O14

I/O15 A-1

BYTE NC

Function Addresses Chip Enable Output Enable Write Enable Reset Ready/Busy Output Data Inputs/Outputs I/O15 Data Input/Output, Word Mode A-1 LSB Address Input, Byte Mode Selects Byte or Word Mode No Connect

AT49F008A AT49F008AT AT49F8192A AT49F8192AT

AT49F8192A T TSOP Top View Type 1

A15 1 A14 2 A13 3 A12 4 A11 5 A10 6

A9 7 A8 8 NC 9 NC 10 WE 11 RESET 12 NC 13 NC 14 NC 15 A18 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24
48 A16 47 BYTE 46 GND 45 I/O15 / A-1 44 I/O7 43 I/O14 42 I/O6 41 I/O13 40 I/O5 39 I/O12 38 I/O4 37 VCC 36 I/O11 35 I/O3 34 I/O10 33 I/O2 32 I/O9 31 I/O1 30 I/O8 29 I/O0 28 OE 27 GND 26 CE 25 A0

AT49F8192A T SOIC SOP Top View

NC 1 A18 2 A17 3

A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 CE 12 GND 13 OE 14 I/O0 15 I/O8 16 I/O1 17 I/O9 18 I/O2 19 I/O10 20 I/O3 21 I/O11 22
44 RESET 43 WE 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BYTE 32 GND 31 I/O15 30 I/O7 29 I/O14 28 I/O6 27 I/O13 26 I/O5 25 I/O12 24 I/O4 23 VCC

AT49F008A T TSOP Top View Type 1

A16 1 A15 2 A14 3 A13 4 A12 5 A11 6

A9 7 A8 8 WE 9 RESET 10 NC 11 RDY/BUSY 12 A18 13 A7 14 A6 15 A5 16 A4 17 A3 18 A2 19 A1 20
40 A17 39 GND 38 NC 37 A-1 36 A10 35 I/O7 34 I/O6 33 I/O5 32 I/O4 31 VCC 30 VCC 29 NC 28 I/O3 27 I/O2 26 I/O1 25 I/O0 24 OE 23 GND 22 CE 21 A0

Note:
“•” denotes a white dot marked on the package.

The device is erased by executing the Erase command sequence the device internally controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections the boot block, and the main memory array block. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming lockout feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of volts or less are used. The boot sector is designed to contain user secure code.

For the AT49F8192A T , the BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic “1” or left open, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tristated and the I/O15 pin is used as an input for the LSB A-1 address function.
2 AT49F008A T /8192A T

AT49F008A T Block Diagram

AT49F008A T /8192A T

VCC GND

OE WE CE RESET

ADDRESS INPUTS

CONTROL LOGIC

Y DECODER X DECODER

AT49F008A

DATA INPUTS/OUTPUTS I/O0 - I/O7
AT49F008A Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT49F008A-70TI

AT49F008A-90TI
AT49F8192A T Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT49F8192A-70TI

AT49F8192AT-70TI

AT49F8192A-90TI

AT49F8192AT-90RI

AT49F8192AT-90TI

Package 40T

Operation Range Industrial
-40° to 85°C Industrial
-40° to 85°C

Package 48T
44R 48T

Operation Range Industrial
-40° to 85°C Industrial
-40° to 85°C Industrial
-40° to 85°C Industrial
-40° to 85°C

Package Type
44-lead, Wide, Plastic Gull Wing Small Outline Package SOIC
40-lead, Plastic Thin Small Outline Package TSOP
48-lead, Plastic Thin Small Outline Package TSOP
14 AT49F008A T /8192A T

Packaging Information
44R SOIC

AT49F008A T /8192A T

Dimensions in Millimeters and Inches . Controlling dimension Inches.

PIN 1
0º ~ 8º

TITLE 2325 Orchard Parkway 44R, 44-lead Body Plastic Gull Wing Small Outline SOIC R San Jose, CA 95131
04/11/01
40T TSOP

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation CD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

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Datasheet ID: AT49F8192AT-70TI 518689