AT49BV642DT-70TU

AT49BV642DT-70TU Datasheet


The AT49BV642D T is a 2.7-volt 64-megabit Flash memory organized as 4,194,304 words of 16 bits each. The memory is divided into 135 sectors for erase operations. The device can be read or reprogrammed off a single 2.7V power supply, making it ideally suited for in-system programming.

Part Datasheet
AT49BV642DT-70TU AT49BV642DT-70TU AT49BV642DT-70TU (pdf)
Related Parts Information
AT49BV642D-70TU-T AT49BV642D-70TU-T AT49BV642D-70TU-T
AT49BV642D-70TU AT49BV642D-70TU AT49BV642D-70TU
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• Single Voltage Operation Read/Write 2.65V - 3.6V
• 2.7V - 3.6V Read/Write
• Access Time 70 ns
• Sector Erase Architecture

One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout Eight 4K Word Sectors with Individual Write Lockout
• Fast Word Program Time 10 µs
• Typical Sector Erase Time 32K Word Sectors 500 ms 4K Word Sectors 100 ms
• Suspend/Resume Feature for Erase and Program Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation 10 mA Active 15 µA Standby
• Data Polling and Toggle Bit for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program Operations
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP Package
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Common Flash Interface CFI
• Green Pb/Halide-free Packaging

The AT49BV642D T is a 2.7-volt 64-megabit Flash memory organized as 4,194,304 words of 16 bits each. The memory is divided into 135 sectors for erase operations. The device can be read or reprogrammed off a single 2.7V power supply, making it ideally suited for in-system programming.

To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. The end of program or erase is detected by Data Polling or toggle bit.

The VPP pin provides data protection and faster programming times. When the VPP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 10.0V, the program dual-word program command operation is accelerated.

A six-word command Enter Single Pulse Program Mode to remove the requirement of entering the three-word program sequence is offered to further improve programming time. After entering the six-word code, only single pulses on the write control lines are required for writing into the device. This mode Single Pulse Word Program is exited by powering down the device, by taking the RESET pin to GND or by a highto-low transition on the VPP input. Erase, Erase Suspend/Resume, Program Suspend/Resume and Read Reset commands will not work while in this mode if entered they will result in data being programmed into the device. It is not recommended that the six-word code reside in the software of the final product but only exist in external programming code.
64-megabit 4M x 16 3-volt Only Flash Memory AT49BV642D AT49BV642DT Not Recommended for New Design

Pin Configurations

Pin Name I/O0 - I/O15 A0 - A21 CE OE WE RESET

VCCQ

TSOP Top View Type 1

Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Reset Write Protection and Power Supply for Accelerated Program Operations Output Power Supply

A15 1 A14 2 A13 3 A12 4 A11 5 A10 6

A9 7 A8 8 A21 9 A20 10 WE 11 RESET 12 VPP 13 NC 14 A19 15 A18 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24
48 A16 47 VCCQ 46 GND 45 I/O15 44 I/O7 43 I/O14 42 I/O6 41 I/O13 40 I/O5 39 I/O12 38 I/O4 37 VCC 36 I/O11 35 I/O3 34 I/O10 33 I/O2 32 I/O9 31 I/O1 30 I/O8 29 I/O0 28 OE 27 GND 26 CE 25 A0
2 AT49BV642D T

Device Operation

AT49BV642D T

Command Sequences

The device powers on in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. After the completion of a program or an erase cycle, the device enters the read mode. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. The address is latched on the falling edge of the WE or CE pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences.

Read

The AT49BV642D T is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

Reset

A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read or standby mode, depending upon the state of the control pins.

Erase

Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical The entire memory can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.

Chip Erase

Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. After the full chip erase the device will return back to the read mode. The hardware reset during Chip Erase will stop the erase but the data will be of unknown state. Any command during Chip Erase except Erase Suspend will be ignored.

Sector Erase

As an alternative to a full chip erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector whose address is valid at the sixth falling edge of WE will be erased provided the given sector has not been protected.

Word Programming

The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The programming address and data are latched in the fourth cycle. The device will automatically generate the required internal programming pulses. Please note that a “0” cannot be programmed back to a “1” only erase operations can convert “0”s to “1”s.

Sector Lockdown

Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated any sector’s usage as a write-protected region is optional to the user.

At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed.

Sector Lockdown Detection A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode see “Software Product Identification Entry/Exit” sections on page 23 , a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation.

Sector Lockdown Override The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed.

Program/Erase Status

The device provides several bits to determine the status of a program or erase operation I/O2, I/O3, I/O5, I/O6, and I/O7. All other status bits are don’t care. The “Status Bit Table” on page 10 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the AT49BV642D T contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, “00” or If the configuration register is set to “00”, the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a “01”, a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value after power-up for the configuration register is Using the four-bus cycle set configuration register command as shown in the “Command Definition Table” on page 11, the value of the configuration register can be changed. Voltages applied to the reset pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below.
4 AT49BV642D T
Ordering Information

Green Package Pb/Halide-free/RoHS Compliant
tACC

ICC mA

Active

Standby
Ordering Code

AT49BV642D-70TU

AT49BV642DT-70TU

Package 48T

Operation Range

Industrial -40 to 85C

Package Type
48-lead, Plastic Thin Small Outline Package TSOP
26 AT49BV642D T

Packaging Information
48T TSOP

PIN 1

AT49BV642D T
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation DD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

BASIC

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
48T, 48-lead 12 x 20 mm Package Plastic Thin Small Outline Package, Type I TSOP
10/18/01

History
• Initial Release
28 AT49BV642D T

Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600

Regional Headquarters

Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel 41 26-426-5555 Fax 41 26-426-5500

Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369

Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Atmel Operations

Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 436-4314

Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 436-4314

La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel 33 2-40-18-18-18 Fax 33 2-40-18-19-60
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Datasheet ID: AT49BV642DT-70TU 518680