AT49BV512-12TI

AT49BV512-12TI Datasheet

The AT49BV512 is a 3-volt only, 512K Flash memories organized as 65,536 words of 8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the devices are deselected, the CMOS standby current is less than 50 µA.

Part	Datasheet
AT49BV512-12TI	AT49BV512-12TI (pdf)

Related Parts	Information
AT49BV512-15JC	AT49BV512-15JC
AT49BV512-15TI	AT49BV512-15TI
AT49BV512-15TC	AT49BV512-15TC
AT49BV512-15JI	AT49BV512-15JI
AT49BV512-12TC	AT49BV512-12TC
AT49BV512-12JC	AT49BV512-12JC
AT49BV512-12VC	AT49BV512-12VC
AT49BV512-90VC	AT49BV512-90VC
AT49BV512-70VC	AT49BV512-70VC
AT49BV512-90TC	AT49BV512-90TC
AT49BV512-90TI	AT49BV512-90TI
AT49BV512-90JI	AT49BV512-90JI
AT49BV512-90JC	AT49BV512-90JC

PDF Datasheet Preview
• Single Supply Voltage Range, 2.7V to 3.6V • Single Supply for Read and Write • Fast Read Access Time 70 ns • Internal Program Control and Timer • 8K Bytes Boot Block with Lockout • Fast Erase Cycle Time 10 Seconds • Byte-by-Byte Programming 30 µs/Byte Typical • Hardware Data Protection • DATA Polling for End of Program Detection • Low Power Dissipation 25 mA Active Current 50 µA CMOS Standby Current • Typical 10,000 Write Cycles The AT49BV512 is a 3-volt only, 512K Flash memories organized as 65,536 words of 8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the devices are deselected, the CMOS standby current is less than 50 µA. To allow for simple in-system reprogrammability, the AT49BV512 does not require high input voltages for programming. Three-volt only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing 512K 64K x 8 Single 2.7-volt Battery-Voltage Flash Memory AT49BV512 Pin Configurations Pin Name A0 - A15 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect VSOP Top View 8 x 14 mm or TSOP Top View 8 x 20 mm Type 1 A11 1 A9 2 A8 3 A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 NC 10 A15 11 A12 12 A7 13 A6 14 A5 15 A4 16 32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3 I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20 DIP Top View NC 1 NC 2 A15 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16 32 VCC 31 WE 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 PLCC Top View 4 A12 3 A15 2 NC 1 NC 32 VCC 31 WE 30 NC A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 Block Diagram Device Operation the entire 1 megabit of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. VCC GND OE WE CE ADDRESS INPUTS OE, CE AND WE LOGIC Y DECODER X DECODER DATA INPUTS/OUTPUTS I/O0 - I/O7 DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING MAIN MEMORY 56K BYTES OPTIONAL BOOT BLOCK 8K BYTES FFFFH 2000H 1FFFH 0000H READ The AT49BV512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. Ordering Information 1 tACC ns ICC mA Active Standby Ordering Code Package Operation Range AT49BV512-70JC AT49BV512-70PC AT49BV512-70TC AT49BV512-70VC 32J 32P6 32T 32V Commercial 0°C - 70°C AT49BV512-70JI AT49BV512-70PI AT49BV512-70TI AT49BV512-70VI 32J 32P6 32T 32V Industrial -40°C - 85°C AT49BV512-90JC AT49BV512-90PC AT49BV512-90TC AT49BV512-90VC 32J 32P6 32T 32V Commercial 0°C - 70°C AT49BV512-90JI AT49BV512-90PI AT49BV512-90TI AT49BV512-90VI 32J 32P6 32T 32V Industrial -40°C - 85°C AT49BV512-12JC AT49BV512-12PC AT49BV512-12TC AT49BV512-12VC 32J 32P6 32T 32V Commercial 0°C - 70°C AT49BV512-12JI AT49BV512-12PI AT49BV512-12TI AT49BV512-12VI 32J 32P6 32T 32V Industrial -40°C - 85°C AT49BV512-15JC AT49BV512-15PC The AT49BV512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range i.e., 0000H to 1FFFH . Users requiring boot block protection to be in the higher address range should contact Atmel. 32J 32P6 32T 32V Package Type 32-lead, Plastic J-leaded Chip Carrier Package PLCC 32-lead, Wide, Plastic Dual Inline Package PDIP 32-lead, Thin Small Outline Package TSOP 8 x 20 mm 32-lead, Thin Small Outline Package VSOP 8 x 14 mm 12 AT49BV512 Packaging Information 32J PLCC AT49BV512 PIN NO. 1 IDENTIFIER e D1 D B1 E2 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. SYMBOL MIN NOM MAX NOTE Note 2 Note 2 10/04/01 TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131 32P6 PDIP D PIN 1 SEATING PLANE 0º ~ 15º REF Note Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed mm COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Note 1 Note 1 TITLE 2325 Orchard Parkway 32P6, 32-lead mm Wide Plastic Dual R San Jose, CA 95131 Inline Package PDIP 09/28/01 32P6 14 AT49BV512 32T TSOP AT49BV512 PIN 1 0º ~ 8º c Pin 1 Identifier SEATING PLANE GAGE PLANE This package conforms to JEDEC reference MO-142, Variation BD. Dimensions D1 and E do not include mold protrusion. Allowable

PDF Datasheet Preview

• Single Supply Voltage Range, 2.7V to 3.6V
• Single Supply for Read and Write
• Fast Read Access Time 70 ns
• Internal Program Control and Timer
• 8K Bytes Boot Block with Lockout
• Fast Erase Cycle Time 10 Seconds
• Byte-by-Byte Programming 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling for End of Program Detection
• Low Power Dissipation
25 mA Active Current 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles

The AT49BV512 is a 3-volt only, 512K Flash memories organized as 65,536 words of 8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the devices are deselected, the CMOS standby current is less than 50 µA.

To allow for simple in-system reprogrammability, the AT49BV512 does not require high input voltages for programming. Three-volt only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing
512K 64K x 8 Single 2.7-volt Battery-Voltage Flash Memory

AT49BV512

Pin Configurations

Pin Name A0 - A15 CE OE WE I/O0 - I/O7 NC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect

VSOP Top View 8 x 14 mm or TSOP Top View 8 x 20 mm Type 1

A11 1 A9 2 A8 3

A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 NC 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20

DIP Top View

NC 1 NC 2 A15 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16
32 VCC 31 WE 30 NC 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3

PLCC Top View
4 A12 3 A15 2 NC 1 NC 32 VCC 31 WE 30 NC

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

Block Diagram Device Operation
the entire 1 megabit of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.

VCC GND

OE WE CE

ADDRESS INPUTS

OE, CE AND WE LOGIC

Y DECODER

X DECODER

DATA INPUTS/OUTPUTS I/O0 - I/O7

DATA LATCH

INPUT/OUTPUT BUFFERS

Y-GATING

MAIN MEMORY 56K BYTES

OPTIONAL BOOT BLOCK 8K BYTES

FFFFH
2000H 1FFFH
0000H

READ The AT49BV512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
Ordering Information 1
tACC ns

ICC mA

Active

Standby
Ordering Code

Package

Operation Range

AT49BV512-70JC

AT49BV512-70PC

AT49BV512-70TC

AT49BV512-70VC
32J 32P6 32T 32V

Commercial 0°C - 70°C

AT49BV512-70JI

AT49BV512-70PI

AT49BV512-70TI

AT49BV512-70VI
32J 32P6 32T 32V

Industrial -40°C - 85°C

AT49BV512-90JC

AT49BV512-90PC

AT49BV512-90TC

AT49BV512-90VC
32J 32P6 32T 32V

Commercial 0°C - 70°C

AT49BV512-90JI

AT49BV512-90PI

AT49BV512-90TI

AT49BV512-90VI
32J 32P6 32T 32V

Industrial -40°C - 85°C

AT49BV512-12JC

AT49BV512-12PC

AT49BV512-12TC

AT49BV512-12VC
32J 32P6 32T 32V

Commercial 0°C - 70°C

AT49BV512-12JI

AT49BV512-12PI

AT49BV512-12TI

AT49BV512-12VI
32J 32P6 32T 32V

Industrial -40°C - 85°C

AT49BV512-15JC

AT49BV512-15PC
The AT49BV512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range i.e., 0000H to 1FFFH . Users requiring boot block protection to be in the higher address range should contact Atmel.
32J 32P6 32T 32V

Package Type 32-lead, Plastic J-leaded Chip Carrier Package PLCC 32-lead, Wide, Plastic Dual Inline Package PDIP 32-lead, Thin Small Outline Package TSOP 8 x 20 mm 32-lead, Thin Small Outline Package VSOP 8 x 14 mm
12 AT49BV512

Packaging Information
32J PLCC

AT49BV512

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
32P6 PDIP

D PIN 1

SEATING PLANE
0º ~ 15º REF

Note Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed mm

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

Note 1

Note 1

TITLE 2325 Orchard Parkway 32P6, 32-lead mm Wide Plastic Dual R San Jose, CA 95131 Inline Package PDIP
09/28/01
32P6
14 AT49BV512
32T TSOP

AT49BV512

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation BD. Dimensions D1 and E do not include mold protrusion. Allowable

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT49BV512-12TI Datasheet file may be downloaded here without warranties.

Datasheet ID: AT49BV512-12TI 518674