AT49BV040B-JU

AT49BV040B-JU Datasheet


AT49BV040B

Part Datasheet
AT49BV040B-JU AT49BV040B-JU AT49BV040B-JU (pdf)
Related Parts Information
AT49BV040B-TU AT49BV040B-TU AT49BV040B-TU
AT49BV040B-VU AT49BV040B-VU AT49BV040B-VU
PDF Datasheet Preview
• Single Supply for Read and Write 2.7V to 5.5V
• Fast Read Access Time 70 ns VCC = 2.7V to 3.6V 55 ns VCC = 4.5V to 5.5V
• Internal Program Control and Timer
• Flexible Sector Architecture

One 16K Bytes Boot Sector with Programming Lockout Two 8K Bytes Parameter Sectors Eight Main Memory Sectors One 32K Bytes, Seven 64K Bytes
• Fast Erase Cycle Time 8 Seconds
• Byte-by-Byte Programming 10 µs/Byte Typical
• Hardware Data Protection
• DATA Polling or Toggle Bit for End of Program Detection
• Low Power Dissipation 20 mA Active Current 25 µA CMOS Standby Current for VCC = 2.7V to 3.6V 30 µA CMOS Standby Current for VCC = 4.5V to 5.5V
• Minimum 100,000 Write Cycles
4-megabit 512K x 8 Flash Memory

AT49BV040B

The AT49BV040B is a 2.7V to 5.5V in-system reprogrammable Flash Memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers an access time of 70 ns VCC = 2.7V to 3.6V and an access time of 55 ns VCC = 4.5V to 5.5V . The power dissipation over the industrial temperature range with VCC = 2.7V to 3.6V is 72 mW and is 110 mW with VCC = 4.5V to 5.5V.

When the device is deselected, the CMOS standby current is less than 30 µA. To allow for simple in-system reprogrammability, the AT49BV040B does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV040B is performed by erasing a sector of data and then programming on a byte by byte basis. The byte programming time is a fast 10 µs. The end of a program or erase cycle can be optionally detected by the DATA polling or toggle bit feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 100,000 cycles.

The device is erased by executing a chip erase or a sector erase command sequence the device internally controls the erase operations. The memory array of the AT49BV040B is organized into two 8K byte parameter sectors, eight main memory sectors, and one boot sector.

The device has the capability to protect the data in the boot sector this feature is enabled by a command sequence. The 16K-byte boot sector includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.

Pin Configurations

Pin Name A0 - A18 CE OE WE I/O0 - I/O7
32-lead PLCC Top View

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs
4 A12 3 A15 2 A16 1 A18 32 VCC 31 WE 30 A17

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20
32-lead VSOP or 32-lead TSOP Top View Type 1

A11 1 A9 2 A8 3

A13 4 A14 5 A17 6 WE 7 VCC 8 A18 9 A16 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
2 AT49BV040B
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3

Block Diagram

AT49BV040B

VCC GND

OE WE CE

ADDRESS INPUTS

CONTROL LOGIC

Y DECODER

X DECODER

DATA INPUTS/OUTPUTS I/O7 - I/O0

INPUT/OUTPUT BUFFERS

PROGRAM DATA LATCHES

Y-GATING

MAIN MEMORY SECTOR 8
64K BYTES

MAIN MEMORY SECTOR 7
64K BYTES

MAIN MEMORY SECTOR 6
64K BYTES

MAIN MEMORY SECTOR 5
Ordering Information

Green Package Pb/Halide-free

ICC mA Active
Ordering Code

AT49BV040B-JU

AT49BV040B-TU

AT49BV040B-VU

Package
32J 32T 32V

Operation Range

Industrial -40° to 85° C

Package Type
32-lead, Plastic, J-leaded Chip Carrier Package PLCC
32-lead, Thin Small Outline Package TSOP
32-lead, Thin Small Outline Package VSOP
16 AT49BV040B

Packaging Information
32J PLCC

AT49BV040B

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
32T TSOP

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation BD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC
• Combined the 3V and 5V part into one datasheet BV .
• Removed the speed of the part form the ordering information table.
• Changed the address hold time to 20 ns.
20 AT49BV040B

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Literature Requests

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Printed on recycled paper.
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Datasheet ID: AT49BV040B-JU 518659