AT49BV4096A-90TC

AT49BV4096A-90TC Datasheet

The AT49BV/LV4096A is a 3-volt, 4-megabit Flash memory organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 67 mV at 2.7V read. When deselected, the CMOS standby current is less than 50 µA.

Part	Datasheet
AT49BV4096A-90TC	AT49BV4096A-90TC (pdf)

Related Parts	Information
AT49BV4096A-90TI	AT49BV4096A-90TI

PDF Datasheet Preview
• Single-voltage Read/Write Operation 2.7V to 3.6V BV , 3.0V to 3.6V LV • Fast Read Access Time 70 ns • Internal Erase/Program Control • Sector Architecture One 8K Word 16K Bytes Boot Block with Programming Lockout Two 4K Word 8K Bytes Parameter Blocks One 240K Word 480K Bytes Main Memory Array Block • Fast Sector Erase Time 10 Seconds • Byte-by-byte or Word-by-word Programming 30 µs Typical • Hardware Data Protection • Data Polling for End of Program Detection • Low Power Dissipation 25 mA Active Current 50 µA CMOS Standby Current • Typical 10,000 Write Cycles The AT49BV/LV4096A is a 3-volt, 4-megabit Flash memory organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 67 mV at 2.7V read. When deselected, the CMOS standby current is less than 50 µA. The device contains a user-enabled “boot block” protection feature. The AT49BV/LV4096A locates the boot block at lowest order addresses “bottom boot” . To allow for simple in-system reprogrammability, the AT49BV/LV4096A does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM it has standard CE, OE and WE inputs to avoid bus contention. Reprogramming the AT49BV/LV4096A is performed by first erasing a block of data and then programming on a byte-by-byte or word-by-word basis. 4-megabit 512K x 8/ 256K x 16 Single 2.7-volt Battery-Voltage Flash Memory AT49BV4096A AT49LV4096A Pin Configurations Pin Name Function A0 - A17 Addresses Chip Enable Output Enable Write Enable RESET Reset VPP can be left unconnected or connected to VCC, GND, 5V or 12V. The input has no effect on the operation of the device. I/O0 - I/O15 Data Inputs/Outputs I/O15 A-1 I/O15 Data Input/Output, Word Mode A-1 LSB Address Input, Byte Mode BYTE Selects Byte or Word Mode No Connect AT49BV/LV4096A SOIC SOP VPP 1 NC 2 A17 3 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 CE 12 GND 13 OE 14 I/O0 15 I/O8 16 I/O1 17 I/O9 18 I/O2 19 I/O10 20 I/O3 21 I/O11 22 44 RESET 43 WE 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BYTE 32 GND 31 I/O15/A-1 30 I/O7 29 I/O14 28 I/O6 27 I/O13 26 I/O5 25 I/O12 24 I/O4 23 VCC AT49BV/LV4096A TSOP Top View Type 1 A15 1 A14 2 A13 3 A12 4 A11 5 A10 6 A9 7 A8 8 NC 9 NC 10 WE 11 RESET 12 VPP 13 NC 14 NC 15 NC 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24 48 A16 47 BYTE 46 GND 45 I/O15/A-1 44 I/O7 43 I/O14 42 I/O6 41 I/O13 40 I/O5 39 I/O12 38 I/O4 37 VCC 36 I/O11 35 I/O3 34 I/O10 33 I/O2 32 I/O9 31 I/O1 30 I/O8 29 I/O0 28 OE 27 GND 26 CE 25 A0 The device is erased by executing the Erase command sequence the device internally controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections, the boot block, and the main memory array block. The typical number of program and erase cycles is in excess of 10,000 cycles. The 8K word boot block section includes a reprogramming lock out feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of volts or less are used. The boot sector is designed to contain user secure code. The BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic “1” or left open, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated and the I/O15 pin is used as an input for the LSB A-1 address function. 2 AT49BV/LV4096A Block Diagram Device Operation Ordering Information tACC ICC mA Active Standby Ordering Code AT49LV4096A-70TI AT49BV4096A-90RC AT49BV4096A-90TC AT49BV4096A-90TI AT49BV/LV4096A Package 48T 44R 48T Operation Range Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C Package Type 44-lead, Wide, Plastic Gull Wing Small Outline SOIC 48-lead, 12 x 20 mm, Plastic Thin Small Outline Package TSOP Packaging Information 44R SOIC Dimensions in Millimeters and Inches . Controlling dimension Inches. PIN 1 0º ~ 8º TITLE 2325 Orchard Parkway 44R, 44-lead Body Plastic Gull Wing Small Outline SOIC R San Jose, CA 95131 04/11/01 14 AT49BV/LV4096A 48T TSOP AT49BV/LV4096A PIN 1 0º ~ 8º c Pin 1 Identifier SEATING PLANE GAGE PLANE This package conforms to JEDEC reference MO-142, Variation DD. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 D D1 E L L1 b c e MIN NOM MAX BASIC BASIC NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 48T, 48-lead 12 x 20 mm Package Plastic Thin Small Outline Package, Type I TSOP 10/18/01 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600 Regional Headquarters

PDF Datasheet Preview

• Single-voltage Read/Write Operation 2.7V to 3.6V BV , 3.0V to 3.6V LV
• Fast Read Access Time 70 ns
• Internal Erase/Program Control
• Sector Architecture

One 8K Word 16K Bytes Boot Block with Programming Lockout Two 4K Word 8K Bytes Parameter Blocks One 240K Word 480K Bytes Main Memory Array Block
• Fast Sector Erase Time 10 Seconds
• Byte-by-byte or Word-by-word Programming 30 µs Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Low Power Dissipation 25 mA Active Current 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles

The AT49BV/LV4096A is a 3-volt, 4-megabit Flash memory organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 67 mV at 2.7V read. When deselected, the CMOS standby current is less than 50 µA.

The device contains a user-enabled “boot block” protection feature. The AT49BV/LV4096A locates the boot block at lowest order addresses “bottom boot” .

To allow for simple in-system reprogrammability, the AT49BV/LV4096A does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM it has standard CE, OE and WE inputs to avoid bus contention. Reprogramming the AT49BV/LV4096A is performed by first erasing a block of data and then programming on a byte-by-byte or word-by-word basis.
4-megabit 512K x 8/ 256K x 16 Single 2.7-volt Battery-Voltage Flash Memory

AT49BV4096A AT49LV4096A

Pin Configurations

Pin Name

Function

A0 - A17

Addresses

Chip Enable

Output Enable

Write Enable

RESET

Reset

VPP can be left unconnected or connected to VCC, GND, 5V or 12V. The input has no effect on the operation of the device.

I/O0 - I/O15

Data Inputs/Outputs

I/O15 A-1

I/O15 Data Input/Output, Word Mode A-1 LSB Address Input, Byte Mode

BYTE

Selects Byte or Word Mode

No Connect

AT49BV/LV4096A SOIC SOP

VPP 1 NC 2 A17 3 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 CE 12

GND 13 OE 14 I/O0 15 I/O8 16 I/O1 17 I/O9 18 I/O2 19

I/O10 20 I/O3 21

I/O11 22
44 RESET 43 WE 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BYTE 32 GND 31 I/O15/A-1 30 I/O7 29 I/O14 28 I/O6 27 I/O13 26 I/O5 25 I/O12 24 I/O4 23 VCC

AT49BV/LV4096A TSOP Top View Type 1

A15 1 A14 2 A13 3 A12 4 A11 5 A10 6

A9 7 A8 8 NC 9 NC 10 WE 11 RESET 12 VPP 13 NC 14 NC 15 NC 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24
48 A16 47 BYTE 46 GND 45 I/O15/A-1 44 I/O7 43 I/O14 42 I/O6 41 I/O13 40 I/O5 39 I/O12 38 I/O4 37 VCC 36 I/O11 35 I/O3 34 I/O10 33 I/O2 32 I/O9 31 I/O1 30 I/O8 29 I/O0 28 OE 27 GND 26 CE 25 A0

The device is erased by executing the Erase command sequence the device internally controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections, the boot block, and the main memory array block. The typical number of program and erase cycles is in excess of 10,000 cycles.

The 8K word boot block section includes a reprogramming lock out feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of volts or less are used. The boot sector is designed to contain user secure code.

The BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic “1” or left open, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated and the I/O15 pin is used as an input for the LSB A-1 address function.
2 AT49BV/LV4096A

Block Diagram Device Operation
Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT49LV4096A-70TI

AT49BV4096A-90RC AT49BV4096A-90TC AT49BV4096A-90TI

AT49BV/LV4096A

Package 48T
44R 48T

Operation Range Industrial
-40° to 85°C Commercial 0° to 70°C

Industrial -40° to 85°C

Package Type
44-lead, Wide, Plastic Gull Wing Small Outline SOIC
48-lead, 12 x 20 mm, Plastic Thin Small Outline Package TSOP

Packaging Information
44R SOIC

Dimensions in Millimeters and Inches . Controlling dimension Inches.

PIN 1
0º ~ 8º

TITLE 2325 Orchard Parkway 44R, 44-lead Body Plastic Gull Wing Small Outline SOIC R San Jose, CA 95131
04/11/01
14 AT49BV/LV4096A
48T TSOP

AT49BV/LV4096A

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation DD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

BASIC

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
48T, 48-lead 12 x 20 mm Package Plastic Thin Small Outline Package, Type I TSOP
10/18/01

Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600

Regional Headquarters

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Datasheet ID: AT49BV4096A-90TC 518649