AT49BV040-90JC

AT49BV040-90JC Datasheet

The AT49BV/LV040 are 3-volt only, 4-megabit Flash memories organized as 524,288 words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 µA.

Part	Datasheet
AT49BV040-90JC	AT49BV040-90JC (pdf)

Related Parts	Information
AT49BV040-90VC	AT49BV040-90VC
AT49LV040-90TC	AT49LV040-90TC
AT49LV040-90VI	AT49LV040-90VI
AT49LV040-90TI	AT49LV040-90TI
AT49BV040-12VC	AT49BV040-12VC
AT49LV040-90VC	AT49LV040-90VC
AT49LV040-90JI	AT49LV040-90JI
AT49BV040-12VI	AT49BV040-12VI
AT49BV040-12TI	AT49BV040-12TI
AT49BV040-12TC	AT49BV040-12TC
AT49BV040-12JI	AT49BV040-12JI
AT49BV040-12JC	AT49BV040-12JC
AT49LV040-90JC	AT49LV040-90JC
AT49LV040-70TI	AT49LV040-70TI
AT49BV040-90VI	AT49BV040-90VI
AT49BV040-90JI	AT49BV040-90JI
AT49BV040-90TC	AT49BV040-90TC
AT49BV040-90TI	AT49BV040-90TI
AT49LV040-70JI	AT49LV040-70JI
AT49LV040-70VI	AT49LV040-70VI
AT49LV040-70VC	AT49LV040-70VC
AT49LV040-70TC	AT49LV040-70TC
AT49LV040-70JC	AT49LV040-70JC

PDF Datasheet Preview
• Single Voltage for Read and Write 2.7V to 3.6V BV , 3.0V to 3.6V LV • Fast Read Access Time 70 ns • Internal Program Control and Timer • 16K Bytes Boot Block with Lockout • Fast Chip Erase Cycle Time 10 seconds • Byte-by-byte Programming 30 µs/Byte Typical • Hardware Data Protection • Data Polling for End of Program Detection • Low Power Dissipation 25 mA Active Current 50 µA CMOS Standby Current • Typical 10,000 Write Cycles • Small Packaging 8 x 14 mm VSOP/TSOP The AT49BV/LV040 are 3-volt only, 4-megabit Flash memories organized as 524,288 words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 µA. The device contains a user-enabled “boot block” protection feature. The AT49BV/LV040 locates the boot block at lowest order addresses “bottom boot” . continued 4-megabit 512K x 8 Single 2.7-volt Battery-Voltage Flash Memory AT49BV040 AT49LV040 I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20 Pin Configurations Pin Name A0 - A18 CE OE WE I/O0 - I/O7 Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs PLCC Top View 4 A12 3 A15 2 A16 1 A18 32 VCC 31 WE 30 A17 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 VSOP Top View 8 x 14 mm or TSOP Top View 8 x 20 mm A11 1 A9 2 A8 3 A13 4 A14 5 A17 6 WE 7 VCC 8 A18 9 A16 10 A15 11 A12 12 A7 13 A6 14 A5 15 A4 16 32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3 To allow for simple in-system reprogrammability, the AT49BV/LV040 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV040 is performed by erasing the entire four megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the Data Polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 16K bytes boot block section includes a reprogramming write lockout feature to provide data integrity. The boot sector is designed to contain user-secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. Block Diagram VCC GND OE WE CE ADDRESS INPUTS OE, CE, AND WE LOGIC Y DECODER X DECODER DATA INPUTS/OUTPUTS I/O7 - I/O0 DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING MAIN MEMORY 496K BYTES OPTIONAL BOOT BLOCK 16K BYTES 7FFFFH 04000H 03FFFH Device Operation READ The AT49BV/LV040 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the highimpedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. ERASURE Before a byte can be reprogrammed, the 512K bytes memory array or 496K bytes if the boot block featured is used must be erased. The erased state of the memory bits is a logical The entire device can be erased at one time by using a six-byte software code. The software chip erase code consists of six-byte load commands to specific address locations with a specific data pattern please refer to “Chip Erase Cycle Waveforms” on page After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. AT49BV/LV040 Ordering Information tACC ICC mA Active Standby Ordering Code AT49BV040-90JC AT49BV040-90TC AT49BV040-90VC AT49BV040-90JI AT49BV040-90TI AT49BV040-90VI AT49BV040-12JC AT49BV040-12TC AT49BV040-12VC AT49BV040-12JI AT49BV040-12TI AT49BV040-12VI AT49LV040-70JC AT49LV040-70TC AT49LV040-70VC AT49LV040-70JI AT49LV040-70TI AT49LV040-70VI AT49LV040-90JC AT49LV040-90TC AT49LV040-90VC AT49LV040-90JI AT49LV040-90TI AT49LV040-90VI AT49BV/LV040 Package 32J 32T 32V 32J 32T 32V 32J 32T 32V 32J 32T 32V 32J 32T 32V 32J 32T 32V 32J 32T 32V 32J 32T 32V Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Package Type 32-lead, Plastic J-leaded Chip Carrier Package PLCC 32-lead, Plastic Thin Small Outline Package TSOP 8 x 20 mm 32-lead, Plastic Thin Small Outline Package TSOP 8 x 14 mm Packaging Information 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

PDF Datasheet Preview

• Single Voltage for Read and Write 2.7V to 3.6V BV , 3.0V to 3.6V LV
• Fast Read Access Time 70 ns
• Internal Program Control and Timer
• 16K Bytes Boot Block with Lockout
• Fast Chip Erase Cycle Time 10 seconds
• Byte-by-byte Programming 30 µs/Byte Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Low Power Dissipation
25 mA Active Current 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Small Packaging 8 x 14 mm VSOP/TSOP

The AT49BV/LV040 are 3-volt only, 4-megabit Flash memories organized as 524,288 words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 µA.

The device contains a user-enabled “boot block” protection feature. The AT49BV/LV040 locates the boot block at lowest order addresses “bottom boot” .
continued
4-megabit 512K x 8 Single 2.7-volt Battery-Voltage Flash Memory

AT49BV040 AT49LV040

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20

Pin Configurations

Pin Name A0 - A18 CE OE WE I/O0 - I/O7

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs

PLCC Top View
4 A12 3 A15 2 A16 1 A18 32 VCC 31 WE 30 A17

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

VSOP Top View 8 x 14 mm or TSOP Top View 8 x 20 mm

A11 1 A9 2 A8 3

A13 4 A14 5 A17 6 WE 7 VCC 8 A18 9 A16 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3

To allow for simple in-system reprogrammability, the AT49BV/LV040 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV040 is performed by erasing the entire four megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the Data Polling feature.

Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 16K bytes boot block section includes a reprogramming write lockout feature to provide data integrity. The boot sector is designed to contain user-secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.

Block Diagram

VCC GND

OE WE CE

ADDRESS INPUTS

OE, CE, AND WE LOGIC

Y DECODER X DECODER

DATA INPUTS/OUTPUTS I/O7 - I/O0

DATA LATCH

INPUT/OUTPUT BUFFERS

Y-GATING

MAIN MEMORY 496K BYTES

OPTIONAL BOOT BLOCK 16K BYTES
7FFFFH
04000H 03FFFH

Device Operation

READ The AT49BV/LV040 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the highimpedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

ERASURE Before a byte can be reprogrammed, the 512K bytes memory array or 496K bytes if the boot block featured is used must be erased. The erased state of the memory bits is a logical The entire device can be erased at one time by using a six-byte software code. The software chip erase code consists of six-byte load commands to specific address locations with a specific data pattern please refer to “Chip Erase Cycle Waveforms” on page

After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased.
AT49BV/LV040 Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code

AT49BV040-90JC

AT49BV040-90TC

AT49BV040-90VC

AT49BV040-90JI AT49BV040-90TI AT49BV040-90VI

AT49BV040-12JC

AT49BV040-12TC

AT49BV040-12VC

AT49BV040-12JI AT49BV040-12TI AT49BV040-12VI

AT49LV040-70JC

AT49LV040-70TC

AT49LV040-70VC

AT49LV040-70JI AT49LV040-70TI AT49LV040-70VI

AT49LV040-90JC

AT49LV040-90TC

AT49LV040-90VC

AT49LV040-90JI AT49LV040-90TI AT49LV040-90VI

AT49BV/LV040

Package
32J 32T 32V
32J 32T 32V
32J 32T 32V
32J 32T 32V
32J 32T 32V
32J 32T 32V
32J 32T 32V
32J 32T 32V

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C

Package Type
32-lead, Plastic J-leaded Chip Carrier Package PLCC
32-lead, Plastic Thin Small Outline Package TSOP 8 x 20 mm
32-lead, Plastic Thin Small Outline Package TSOP 8 x 14 mm

Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

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Datasheet ID: AT49BV040-90JC 518643