MAX24287EVKIT

MAX24287EVKIT Datasheet

MAX24287 1Gbps Parallel-to-Serial MII Converter

Part	Datasheet
MAX24287EVKIT	MAX24287EVKIT (pdf)

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MAX24287 1Gbps Parallel-to-Serial MII Converter The MAX24287 is a flexible, low-cost Ethernet interface conversion IC. The parallel interface can be configured for GMII, RGMII, TBI, RTBI, or 10/100 MII, while the serial interface can be configured for 1.25Gbps SGMII or 1000BASE-X operation. In SGMII mode, the device interfaces directly to Ethernet switch ICs, ASIC MACs, and 1000BASE-T electrical SFP modules. In 1000BASE-X mode, the device interfaces directly to 1Gbps 1000BASE-X SFP optical modules. The MAX24287 performs automatic translation of link speed and duplex autonegotiation between parallel MII MDIO and the serial interface. Microprocessor interaction is optional for device operation. Hardware-configured modes support SGMII master and 1000BASE-X autonegotiation without software involvement. This device is ideal for interfacing single-channel GMII/MII devices such as microprocessors, FPGAs, network processors, Ethernet-over-SONET or -PDH mappers, and TDM-over-packet circuit emulation devices. The device also provides a convenient solution to interface such devices with electrical or optical Ethernet SFP modules. Any System with a Need to Interface a Component with a Parallel MII Interface GMII, RGMII, TBI RTBI, 10/100 MII to a Component with an SGMII or 1000BASE-X Interface Switches and Routers Telecom Equipment Ordering Information PART MAX24287ETK+ TEMP RANGE -40°C to +85°C PIN-PACKAGE 68 TQFN-EP* +Denotes a lead Pb -free/RoHS-compliant package. *EP = Exposed pad. Block Diagram appears on page Register Map appears on page Highlighted Features Bidirectional Wire-Speed Ethernet Interface Conversion Can Interface Directly to SFP Modules and SGMII PHY and Switch ICs Parallel Interface Configurable as GMII, RGMII, TBI, RTBI, or 10/100 MII Serial Interface Has Clock and Data Recovery Block CDR and Does Not Require a Clock Input Translates Link Speed and Duplex Mode Negotiation Between MDIO and SGMII PCS Supports 10/100 MII or RGMII Operation with SGMII Running at the Same Rate Configurable for 10/100 MII DTE or DCE Modes i.e., Connects to PHY or MAC Can Also Be Configured as General-Purpose 1:10 SerDes with Optional Comma Alignment Supports Synchronous Ethernet by Providing a 25MHz or 125MHz Recovered Clock and Accepting a Transmit Clock Can Provide a 125MHz Clock for the MAC to Use as GTXCLK Accepts 10MHz, 12.8MHz, 25MHz or 125MHz Reference Clock Can Be Pin-Configured at Reset for Many Common Usage Scenarios Optional Software Control Through MDIO Interface GPIO Pins Can Be Configured as Clocks, Status Signals and Interrupt Outputs 1.2V Operation with 3.3V I/O Small, 8mm x 8mm, 68-Pin TQFN Package Maxim Integrated Products 1 MAX24287 Table of Contents APPLICATION BLOCK DIAGRAM DETAILED FEATURES ACRONYMS, ABBREVIATIONS, AND GLOSSARY PIN DESCRIPTIONS FUNCTIONAL DESCRIPTION PIN CONFIGURATION DURING RESET GENERAL-PURPOSE I/O Receive Recovered Clock Squelch Criteria 18 RESET AND PROCESSOR INTERRUPT Reset 18 Processor 18 MDIO INTERFACE MDIO Overview 19 Examples of MAX24287 and PHY Management Using MDIO 21 SERIAL INTERFACE 1000BASE-X OR SGMII PARALLEL INTERFACE GMII, RGMII, TBI, RTBI, GMII Mode 24 TBI 25 RGMII Mode 26 RTBI Mode 28 MII Mode 29 AUTO-NEGOTIATION 1000BASE-X Auto-Negotiation 30 SGMII Control Information Transfer 32 DATA PATHS GMII, RGMII and MII Serial to Parallel Conversion and Decoding 35 GMII, RGMII and MII Parallel to Serial Conversion and Encoding 35 TBI, RTBI Serial to Parallel Conversion and Decoding 35 TBI Parallel to Serial Conversion and Encoding 35 Rate Adaption Buffers, Jumbo Packets and Clock Frequency 35 TIMING RX PLL 37 TX PLL 37 Input Jitter Tolerance 37 Output Jitter 37 TX PLL Jitter Transfer 37 GPIO Pins as Clock 38 Diagnostic 38 Terminal 38 Remote Loopback 38 DIAGNOSTIC AND TEST FUNCTIONS DATA PATH LATENCIES BOARD DESIGN RECOMMENDATIONS REGISTER DESCRIPTIONS REGISTER MAP REGISTER MAX24287 42 BMSR 43 ID1 and ID2 44 AN_ADV 45 AN_RX 45 AN_EXP 45 EXT_STAT 46 JIT_DIAG 46 47 GMIICR 48 CR 49 50 PAGESEL 51 52 GPIOCR1 52 GPIOCR2 52 GPIOSR 53 JTAG AND BOUNDARY SCAN JTAG DESCRIPTION JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION JTAG INSTRUCTION REGISTER AND INSTRUCTIONS JTAG TEST REGISTERS ELECTRICAL RECOMMENDED OPERATING CONDITIONS DC ELECTRICAL CHARACTERISTICS CMOS/TTL DC Characteristics 59 SGMII/1000BASE-X DC 59 AC ELECTRICAL CHARACTERISTICS REFCLK AC Characteristics 60 SGMII/1000BASE-X Interface Receive AC 60 SGMII/1000BASE-X Interface Transmit AC 60 Parallel Interface Receive AC Characteristics 61 Parallel Interface Transmit AC Characteristics 63 MDIO Interface AC Characteristics 65 JTAG Interface AC Characteristics 66 PIN ASSIGNMENTS PACKAGE AND THERMAL INFORMATION MAX24287 List of Figures Figure Block Diagram 7 Figure MDIO Slave State Machine 20 Figure Management Information Flow Options, Case 1,Tri-Mode 21 Figure Management Information Flow Options, Case 2, SGMII Switch Chip 21 Figure Management Information Flow Options, Case 3, 1000BASE-X Interface 22 Figure Recommended External Components for High-Speed Serial Interface 23 Figure Auto-Negotiation with a Link Partner over 1000BASE-X 31 Figure 1000BASE-X Auto-Negotiation tx_Config_Reg and rx_Config_Reg Fields 31 Figure SGMII Control Information Generation, Reception and 33 Figure SGMII tx_Config_Reg and rx_Config_Reg Fields 33 Figure Timing Path 36 Figure Recommended REFCLK Oscillator Wiring 40 Figure JTAG Block 54 Figure JTAG TAP Controller State Machine 56 Figure MII/GMII/RGMII/TBI/RTBI Receive Timing Waveforms 61 Figure MII/GMII/RGMII/TBI/RTBI Transmit Timing Waveforms 63 Figure MDIO Interface Timing 65 Figure JTAG Timing 66 MAX24287 List of Tables Table Pin Type 8 Table Detailed Pin Descriptions Global Pins 3 Pins 8 Table Detailed Pin Descriptions MDIO Interface 2 Pins 9 Table Detailed Pin Descriptions JTAG Interface 5 pins 9 Table Detailed Pin Descriptions GPIO signals 5 dedicated pins, 4 shared pins 9 Table Detailed Pin Descriptions SGMII/1000BASE-X Serial Interface 7 pins 10 Table Detailed Pin Descriptions Parallel Interface 25 pins 11 Table Detailed Pin Descriptions Power and Ground Pins 15 Table Reset Configuration Pins, 15-Pin Mode COL=0 16 Table Parallel Interface Configuration 16 Table Reset Configuration Pins, 3-Pin Mode COL=1 17 Table GPO1, GPIO1 and GPIO3 Configuration Options 17 Table GPO2 and GPIO2 Configuration 17 Table GPIO4, GPIO5, GPIO6 and GPIO7 Configuration Options 18 Table Parallel Interface 24 Table GMII Parallel Bus Pin Naming 24 Table TBI Parallel Bus Pin Naming Normal 25 Table TBI Parallel Bus Pin Naming One-Clock Mode 25 Table RGMII Parallel Bus Pin Naming 27 Table RTBI Parallel Bus Pin Naming 28 Table MII Parallel Bus Pin 29 Table AN_ADV 1000BASE-X Auto-Negotiation Ability Advertisement Register MDIO 31 Table AN_RX 1000BASE-X Auto-negotiation Ability Receive Register MDIO 32 Table AN_ADV SGMII Configuration Information Register MDIO 4 34 Table AN_RX SGMII Configuration Information Receive Register MDIO 5 34 Table Timing Path Muxes No Loopback 36 Table Timing Path Muxes DLB Loopback 36 Table Timing Path Muxes RLB Loopback 37 Table GMII Data Path Latencies 39 Table Register Map 41 Table JTAG Instruction Codes 56 Table JTAG ID Code 57 Table Recommended DC Operating Conditions 58 Table DC 58 Table DC Characteristics for Parallel and MDIO Interfaces 59 Table SGMII/1000BASE-X Transmit DC Characteristics 59 Table SGMII/1000BASE-X Receive DC Characteristics 59 Table REFCLK AC Characteristics 60 Table 1000BASE-X and SGMII Receive AC Characteristics 60 Table 1000BASE-X and SGMII Receive Jitter Tolerance 60 Table SGMII and 1000BASE-X Transmit AC Characteristics 60 Table 1000BASE-X Transmit Jitter 60 Table GMII and TBI Receive AC Characteristics 61 Table RGMII-1000 and RTBI Receive AC 62 Table RGMII-10/100 Receive AC Characteristics 62 Table Receive AC Characteristics 62 Table Receive AC Characteristics 63 Table GMII, TBI, RGMII-1000 and RTBI Transmit AC Characteristics 63 Table RGMII-10/100 Transmit AC Characteristics 64 Table Transmit AC Characteristics 64 Table Transmit AC Characteristics 64 Table MDIO Interface AC Characteristics 65 Table JTAG Interface 66 Table Package Thermal Properties, Natural Convection 68 MAX24287 Application Examples a Copper Media Processor, M ASIC, A FPGA C <GMII> RXD[7:0] RX_CLK 125 MHz TXD[7:0] TX_CLK 125 MHz <SGMII> MAX 24287 TD TCLK 625 MHz Optional SGMII PHY b Connect Parallel MII Component to SGMII Component <GMII>

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MAX24287 1Gbps Parallel-to-Serial MII Converter

The MAX24287 is a flexible, low-cost Ethernet interface conversion IC. The parallel interface can be configured for GMII, RGMII, TBI, RTBI, or 10/100 MII, while the serial interface can be configured for 1.25Gbps SGMII or 1000BASE-X operation. In SGMII mode, the device interfaces directly to Ethernet switch ICs, ASIC MACs, and 1000BASE-T electrical SFP modules. In 1000BASE-X mode, the device interfaces directly to 1Gbps 1000BASE-X SFP optical modules. The MAX24287 performs automatic translation of link speed and duplex autonegotiation between parallel MII MDIO and the serial interface. Microprocessor interaction is optional for device operation. Hardware-configured modes support SGMII master and 1000BASE-X autonegotiation without software involvement.

This device is ideal for interfacing single-channel GMII/MII devices such as microprocessors, FPGAs, network processors, Ethernet-over-SONET or -PDH mappers, and TDM-over-packet circuit emulation devices. The device also provides a convenient solution to interface such devices with electrical or optical Ethernet SFP modules.

Any System with a Need to Interface a Component with a Parallel MII Interface GMII, RGMII, TBI RTBI, 10/100 MII to a Component with an SGMII or 1000BASE-X Interface Switches and Routers Telecom Equipment
Ordering Information

PART MAX24287ETK+

TEMP RANGE -40°C to +85°C

PIN-PACKAGE 68 TQFN-EP*
+Denotes a lead Pb -free/RoHS-compliant package. *EP = Exposed pad.

Block Diagram appears on page

Register Map appears on page

Highlighted Features

Bidirectional Wire-Speed Ethernet Interface Conversion

Can Interface Directly to SFP Modules and SGMII PHY and Switch ICs

Parallel Interface Configurable as GMII, RGMII, TBI, RTBI, or 10/100 MII

Serial Interface Has Clock and Data Recovery Block CDR and Does Not Require a Clock Input

Translates Link Speed and Duplex Mode Negotiation Between MDIO and SGMII PCS

Supports 10/100 MII or RGMII Operation with SGMII Running at the Same Rate

Configurable for 10/100 MII DTE or DCE Modes i.e., Connects to PHY or MAC

Can Also Be Configured as General-Purpose 1:10 SerDes with Optional Comma Alignment

Supports Synchronous Ethernet by Providing a 25MHz or 125MHz Recovered Clock and Accepting a Transmit Clock

Can Provide a 125MHz Clock for the MAC to Use as GTXCLK

Accepts 10MHz, 12.8MHz, 25MHz or 125MHz Reference Clock

Can Be Pin-Configured at Reset for Many Common Usage Scenarios

Optional Software Control Through MDIO Interface

GPIO Pins Can Be Configured as Clocks, Status Signals and Interrupt Outputs
1.2V Operation with 3.3V I/O

Small, 8mm x 8mm, 68-Pin TQFN Package

Maxim Integrated Products 1
MAX24287

Table of Contents

APPLICATION

BLOCK DIAGRAM

DETAILED FEATURES

ACRONYMS, ABBREVIATIONS, AND GLOSSARY

PIN DESCRIPTIONS

FUNCTIONAL DESCRIPTION

PIN CONFIGURATION DURING RESET GENERAL-PURPOSE I/O

Receive Recovered Clock Squelch Criteria 18 RESET AND PROCESSOR INTERRUPT

Reset 18 Processor 18 MDIO INTERFACE MDIO Overview 19 Examples of MAX24287 and PHY Management Using MDIO 21 SERIAL INTERFACE 1000BASE-X OR SGMII PARALLEL INTERFACE GMII, RGMII, TBI, RTBI, GMII Mode 24 TBI 25 RGMII Mode 26 RTBI Mode 28 MII Mode 29 AUTO-NEGOTIATION 1000BASE-X Auto-Negotiation 30 SGMII Control Information Transfer 32 DATA PATHS GMII, RGMII and MII Serial to Parallel Conversion and Decoding 35 GMII, RGMII and MII Parallel to Serial Conversion and Encoding 35 TBI, RTBI Serial to Parallel Conversion and Decoding 35 TBI Parallel to Serial Conversion and Encoding 35 Rate Adaption Buffers, Jumbo Packets and Clock Frequency 35 TIMING RX PLL 37 TX PLL 37 Input Jitter Tolerance 37 Output Jitter 37 TX PLL Jitter Transfer 37 GPIO Pins as Clock 38 Diagnostic 38 Terminal 38 Remote Loopback 38 DIAGNOSTIC AND TEST FUNCTIONS DATA PATH LATENCIES BOARD DESIGN RECOMMENDATIONS

REGISTER DESCRIPTIONS

REGISTER MAP REGISTER

MAX24287
42 BMSR 43 ID1 and ID2 44 AN_ADV 45 AN_RX 45 AN_EXP 45 EXT_STAT 46 JIT_DIAG 46 47 GMIICR 48 CR 49 50 PAGESEL 51 52 GPIOCR1 52 GPIOCR2 52 GPIOSR 53

JTAG AND BOUNDARY SCAN

JTAG DESCRIPTION JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION JTAG INSTRUCTION REGISTER AND INSTRUCTIONS JTAG TEST REGISTERS

ELECTRICAL

RECOMMENDED OPERATING CONDITIONS DC ELECTRICAL CHARACTERISTICS

CMOS/TTL DC Characteristics 59 SGMII/1000BASE-X DC 59 AC ELECTRICAL CHARACTERISTICS REFCLK AC Characteristics 60 SGMII/1000BASE-X Interface Receive AC 60 SGMII/1000BASE-X Interface Transmit AC 60 Parallel Interface Receive AC Characteristics 61 Parallel Interface Transmit AC Characteristics 63 MDIO Interface AC Characteristics 65 JTAG Interface AC Characteristics 66

PIN ASSIGNMENTS

PACKAGE AND THERMAL INFORMATION

MAX24287

List of Figures

Figure Block Diagram 7 Figure MDIO Slave State Machine 20 Figure Management Information Flow Options, Case 1,Tri-Mode 21 Figure Management Information Flow Options, Case 2, SGMII Switch Chip 21 Figure Management Information Flow Options, Case 3, 1000BASE-X Interface 22 Figure Recommended External Components for High-Speed Serial Interface 23 Figure Auto-Negotiation with a Link Partner over 1000BASE-X 31 Figure 1000BASE-X Auto-Negotiation tx_Config_Reg and rx_Config_Reg Fields 31 Figure SGMII Control Information Generation, Reception and 33 Figure SGMII tx_Config_Reg and rx_Config_Reg Fields 33 Figure Timing Path 36 Figure Recommended REFCLK Oscillator Wiring 40 Figure JTAG Block 54 Figure JTAG TAP Controller State Machine 56 Figure MII/GMII/RGMII/TBI/RTBI Receive Timing Waveforms 61 Figure MII/GMII/RGMII/TBI/RTBI Transmit Timing Waveforms 63 Figure MDIO Interface Timing 65 Figure JTAG Timing 66

MAX24287

List of Tables

Table Pin Type 8 Table Detailed Pin Descriptions Global Pins 3 Pins 8 Table Detailed Pin Descriptions MDIO Interface 2 Pins 9 Table Detailed Pin Descriptions JTAG Interface 5 pins 9 Table Detailed Pin Descriptions GPIO signals 5 dedicated pins, 4 shared pins 9 Table Detailed Pin Descriptions SGMII/1000BASE-X Serial Interface 7 pins 10 Table Detailed Pin Descriptions Parallel Interface 25 pins 11 Table Detailed Pin Descriptions Power and Ground Pins 15 Table Reset Configuration Pins, 15-Pin Mode COL=0 16 Table Parallel Interface Configuration 16 Table Reset Configuration Pins, 3-Pin Mode COL=1 17 Table GPO1, GPIO1 and GPIO3 Configuration Options 17 Table GPO2 and GPIO2 Configuration 17 Table GPIO4, GPIO5, GPIO6 and GPIO7 Configuration Options 18 Table Parallel Interface 24 Table GMII Parallel Bus Pin Naming 24 Table TBI Parallel Bus Pin Naming Normal 25 Table TBI Parallel Bus Pin Naming One-Clock Mode 25 Table RGMII Parallel Bus Pin Naming 27 Table RTBI Parallel Bus Pin Naming 28 Table MII Parallel Bus Pin 29 Table AN_ADV 1000BASE-X Auto-Negotiation Ability Advertisement Register MDIO 31 Table AN_RX 1000BASE-X Auto-negotiation Ability Receive Register MDIO 32 Table AN_ADV SGMII Configuration Information Register MDIO 4 34 Table AN_RX SGMII Configuration Information Receive Register MDIO 5 34 Table Timing Path Muxes No Loopback 36 Table Timing Path Muxes DLB Loopback 36 Table Timing Path Muxes RLB Loopback 37 Table GMII Data Path Latencies 39 Table Register Map 41 Table JTAG Instruction Codes 56 Table JTAG ID Code 57 Table Recommended DC Operating Conditions 58 Table DC 58 Table DC Characteristics for Parallel and MDIO Interfaces 59 Table SGMII/1000BASE-X Transmit DC Characteristics 59 Table SGMII/1000BASE-X Receive DC Characteristics 59 Table REFCLK AC Characteristics 60 Table 1000BASE-X and SGMII Receive AC Characteristics 60 Table 1000BASE-X and SGMII Receive Jitter Tolerance 60 Table SGMII and 1000BASE-X Transmit AC Characteristics 60 Table 1000BASE-X Transmit Jitter 60 Table GMII and TBI Receive AC Characteristics 61 Table RGMII-1000 and RTBI Receive AC 62 Table RGMII-10/100 Receive AC Characteristics 62 Table Receive AC Characteristics 62 Table Receive AC Characteristics 63 Table GMII, TBI, RGMII-1000 and RTBI Transmit AC Characteristics 63 Table RGMII-10/100 Transmit AC Characteristics 64 Table Transmit AC Characteristics 64 Table Transmit AC Characteristics 64 Table MDIO Interface AC Characteristics 65 Table JTAG Interface 66 Table Package Thermal Properties, Natural Convection 68

MAX24287

Application Examples
a Copper Media

Processor, M ASIC, A FPGA C
<GMII>

RXD[7:0] RX_CLK 125 MHz

TXD[7:0] TX_CLK 125 MHz
<SGMII>

MAX 24287

TD TCLK 625 MHz Optional

SGMII PHY
b Connect Parallel MII Component to SGMII Component
<GMII>

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Datasheet ID: MAX24287EVKIT 647277