DS3134DK

DS3134DK Datasheet

DS3134 Chateau Channelized T1 And

Part	Datasheet
DS3134DK	DS3134DK (pdf)

Related Parts	Information
DS3134	DS3134

PDF Datasheet Preview
DS3134 Chateau Channelized T1 And E1 And HDLC Controller • 256 Channel HDLC Controller that Supports up to 64 T1 or E1 Lines or Two T3 Lines • 256 Independent bi-directional HDLC channels • 16 physical ports 16 Tx & 16 Rx that can be configured as either channelized or unchannelized • Two fast 52 Mbps ports/other ports capable of speeds up to 10 Mbps unchannelized • Channelized Ports 0 to 15 handle one, two or four T1 or E1 lines • Supports up to 64 T1 or E1 data streams • Per channel DS0 loopbacks in both direction • Support transparent Mode • V.54 loopback code detector • Onboard Bit Error Rate Tester BERT with auto error insertion capability • BERT function can be assigned to any HDLC channel or any port • 104 Mbps full duplex throughput • Large 16 kbits FIFO in both receive and transmit directions • Efficient scatter / gather DMA • Receive data packets are Time stamped • Transmit packet priority setting • Local bus allows for PCI bridging or local access • Intel or Motorola bus signals supported • 25 MHz to 33 MHz 32-bit PCI V2.1 backplane interface • 3.3V low power CMOS with 5V tolerant I/O • JTAG support IEEE • 256 Lead Plastic BGA 27 mm x 27 mm The DS3134 Chateau device is a 256-channel HDLC controller. The DS3134 is capable of handling up to 64 T1 or E1 data streams or 2 T3 data streams. Each of the 16 physical ports can handle one, two or four T1 or E1 data streams. The Chateau consists of the following blocks • Layer Block • HDLC Block • FIFO Block • DMA Block • PCI Bus • Local Bus 1 of 203 101600 DS3134 There are 16 HDLC Engines one for each port that are capable of operating at speeds up to Mbps in channelized mode and up to 10 Mbps in unchannelized mode. There are also two Fast HDLC Engines, which only reside on Ports 0 and 1 and they are capable of operating at speeds up to 52 Mbps. Applications/Markets include: • Channelized T1/E1 • Clear channel unchannelized T1/E1 • Channelized T3/E3 • Dual clear channel unchannelized T3/E3 • High density Frame Relay access • xDSL each port can support up to 10 Mbps • Dual HSSI • V.35 • SONET/SDH EOC/ECC Termination • Any applications require large number of HDLC channels The device fully meets the following specifications ANSI American National Standards Institute T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995 and PCI Local Bus Specification V2.1 June 1, ITU Q.921 March 1993 and ISO Standard 3309-1979 Data Communications HDLC Procedures Frame Structure. 2 of 203 DS3134 Version 1/30/98 Original release. Version 2 4/4/98 Assigned signals to leads Section Added more information to Sections 1, 5, 7, and Removed the P3VEN signal pin Section and Added FIFO Priority Control bits to the MC register Section Added Abort and Bit Stuffing Control bits to the RHCD and THCD registers Section Changed the Absolute Maximum Voltage Rating and IOH numbers Section Changed the Low Water Mark definition Section Added Section 14 on Applications. Version 3 6/22/98 Corrected JTRST* lead from V19 to U19 Section Added TEST lead at C3 Section Added the Valid Receive Done Queue Descriptor bit Section Corrected JTAG Device Code from 0000614Ch to 00006143h Section Changed the order of the TABTE & TZSD bits in the THCD Register Section Added JTAG Scan Control Information into Table 11.4A Section Added Minimum Grant & Maximum Latency Settings to PINTL0 Section Remove the HDLC channel restriction that required channels 1 to 128 to be assigned to ports 0 to 7 and HDLC channels 129 to 256 to be assigned to port 8 to 15 Sections 1, and Version 4 11/18/98 Added information about queues full and empty states Sections and Changed BERT ones and zeros detector from 32 consecutive to 31 consecutive Section Changed BERT Bit and Error Counters to count during loss of receive synchronization Section Corrected Table 1E Section Added bit numbers to register descriptions. Changed Local Bus Configuration Mode AC Timing Parameter A7 from 5ns to 40ns. Section Version 5 09/01/99 Typos corrections and add clarifications. Section Change the number of T1/E1 support from 64 to 56 due to design over sight Section 1 Added clarifications for Receive High Water Mark and corrected Transmit Low Water Mark to a value from 1 to smaller or equal to N where N = the number of linked blocks. Removed bit 1 of the RDMAQ register, this function is automatically implemented. Please refer to section page 90 Figure 10.3A signal LRD* is moved back one LCLK cycle to align with the rising edge of LCLK Figure 103B signal LWR* is moved back one LCLK cycle to align with the rising edge of LCLC 3 of 203 4 of 203 TABLE OF CONTENTS DS3134 Section 1: Section 2 Signal 16 Overview / Signal Lead 16 Serial Port Interface Signal 22 Local Bus Signal 24 JTAG Signal 27 PCI Bus Signal 28 Supply & Test Signal 31 Section 3 Memory 32 General Configuration 32 Receive Port 33 Transmit Port 33 Channelized Port 34 HDLC 35 BERT 35 Receive DMA 35 Transmit DMA 36 FIFO 36 PCI Configuration Registers for Function 36 PCI Configuration Registers for Function 37 Section 4 General Device Configuration & 37 Master Reset & ID Register 37 Master Configuration Register 38 Status & 40 Status & Interrupt General 40 Status & Interrupt Register 43 Test Register 50 Section 5 Layer 51 General 51 Port Register 55 Layer One Configuration Register 59 Receive V.54 65 BERT Register 70 Section 6 77 General 77 HDLC Register 79 5 of 203 DS3134 Section 7 85 Bit 6 / PCI Bus Orientation PBO . This bit selects whether HDLC packet data on the PCI Bus will operate in either Little Endian format or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest address while Big Endian places the least significant byte at the highest address. This bit setting only affects HDLC data on the PCI Bus. All other PCI Bus transactions to the internal device configuration registers, PCI configuration registers, and Local Bus, are always in Little Endian format. 0 = HDLC Packet Data on the PCI Bus is in Little Endian format 1 = HDLC Packet Data on the PCI Bus is in Big Endian format 40 of 203 DS3134 Bits 7 to 11 / BERT Port Select Bits 0 to 4 BPS0 to BPS4 . These 5 bits select which port has the dedicated resources of the BERT. = Port 0 00001 = Port 1 00010 = Port 2 00011 = Port 3 00100 = Port 4 00101 = Port 5 00110 = Port 6 00111 = Port 7 01000 = Port 8 01001 = Port 9 01010 = Port 10 01011 = Port 11 01100 = Port 12 01101 = Port 13 01110 = Port 14 01111 = Port 15 10000 = Port 0 hi speed 10001 = Port 1 hi speed 10010 = n/a 10011 = n/a 10100 = n/a 10101 = n/a 10110 = n/a 10111 = n/a 11000 = n/a 11001 = n/a 11010 = n/a 11011 = n/a 11100 = n/a 11101 = n/a 11110 = n/a = n/a Bit 12 / Receive FIFO Priority Control Bit 0 RFPC0 . Bit 13 / Receive FIFO Priority Control Bit 1 RFPC1 . These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest priority to the DMA to transfer data from the FIFO to the PCI Bus. In the priority decoded scheme, the lower the HDLC channel numbers, the higher the priority. 00 = all HDLC channels are serviced Round Robin 01 = HDLC Channels 1 & 2 are Priority Decoded other HDLC Channels are Round Robin 10 = HDLC Channels 1 to 16 are Priority Decoded other HDLC Channels are Round Robin 11 = HDLC Channels 1 to 64 are Priority Decoded other HDLC Channels are Round Robin Bit 14 / Transmit FIFO Priority Control Bit 0 TFPC0 . Bit 15 / Transmit FIFO Priority Control Bit 1 TFPC1 . These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest priority to the DMA to transfer data from the PCI Bus to the FIFO. In the priority decoded scheme, the lower the HDLC channel numbers, the higher the priority. 00 = all HDLC channels are serviced Round Robin 01 = HDLC Channels 1 & 2 are Priority Decoded other HDLC Channels are Round Robin 10 = HDLC Channels 1 to 16 are Priority Decoded other HDLC Channels are Round Robin 11 = HDLC Channels 1 to 64 are Priority Decoded other HDLC Channels are Round Robin STATUS & INTERRUPT Status & Interrupt General Description of Operation There are three status register in the device, Status Master SM , Status for the Receive V54 Loopback Detector SV54 , and Status for DMA SDMA . All three registers report events in real time as they occur by setting a bit within the register to a one. All bits that have been set within the register are cleared when the register is read and the bit will not be set again until the event has occurred again. Each bit has the ability to generate an interrupt at the PCI Bus via the PINTA* output signal pin and if the Local Bus is in the Configuration Mode, then an interrupt will also be created at the LINT* output signal pin. Each status register has an associated Interrupt Mask Register, which can allow/deny interrupts from being generated on a bit-by-bit basis. All status remains active even if the associated Interrupt is disabled. 41 of 203 DS3134 SM Register The Status Master SM register reports events that occur at the Port Interface, at the BERT receiver, at the PCI Bus and at the Local Bus. See Figure 4.3.1A for details. The Port Interface reports Change Of Frame Alignment COFA events. If the software detects that one of these bits as being set, the software must then begin polling the RP[n]CR or TP[n]CR registers of each active port a maximum of 16 reads to determine which port or ports has incurred a COFA. Also via the Interrupt Enable for Receive COFA IERC and Interrupt Enable for Transmit COFA IETC control bits in the RP[n]CR and TP[n]CR registers respectively, the Host can allow/deny the COFA indications to be passed on to the SRCOFA and STCOFA status bits. The BERT receiver will report three events, a change in the receive synchronizer status, a bit error being detected, and if either the Bit Counter or the Error Counter overflows. Each of these events can be masked within the BERT function via the BERT Control Register BERTC0 . If the software detects that the BERT has reported an event has occurred, then the software must read the BERT Status Register BERTEC0 to determine which event s has occurred. The SM register also reports events as they occur in the PCI Bus and the Local Bus. There are no control bits to stop these events from being reported in the SM register. When the Local Bus is operated in the PCI Bridge Mode, SM reports any interrupts detected via the Local Bus LINT* input signal pin and if any timing errors occur because of the use of the external timing signal LRDY*. When the Local Bus is operated in the Configuration Mode, the LBINT and LBE bits are meaningless and should be ignored. SV54 Register The Status for Receive V.54 Detector SV54 register reports if the V.54 loopback detector has either timed out in its search for the V.54 loop up pattern or if the detector has found and verified the loop up/down pattern. There is a separate status bit SLBP for each port. When set, the Host must read the VTO and VLB status bits in the RP[n]CR register of the corresponding port to find the exact state of the V.54 detector. When the V.54 detector experiences a time out in it's search for the loop up code VTO = 1 , then the SLBP status bit will be continuously set until the V.54 detector is reset by the Host toggling the VRST bit in RP[n]CR register. There are no control bits to stop these events from being reported in the SV54 register. See Figure 4.3.1A for details on the status bits and Section 5 for details on the operation of the V.54 loopback detector. SDMA Register The Status for DMA SDMA register reports events that occur regarding the Receive and Transmit DMA blocks as well as the receive HDLC controller and FIFO. The SDMA will report when the DMA reads from either the Receive Free Queue or Transmit Pending Queue or writes to the Receive or Transmit Done Queues. Also reported are error conditions that might occur in the access of one of these queues. The SDMA will report if any of the HDLC channels experiences a FIFO overflow/underflow condition and if the receive HDLC controller encounters a CRC error, abort signal, or octet length problem on any of the HDLC channels. The Host can determine which specific HDLC channel incurred a FIFO overflow/underflow, CRC error, octet length error or abort by reading the status bits as reported in Done Queues which are created by the DMA. There are no control bits to stop these events from being reported in the SDMA register. 42 of 203 DS3134 STATUS REGISTER BLOCK DIAGRAM FOR SM & SV54 Figure 4.3.1A BERT Transmit Receive BERTEC0 Bit 1 BECO BERTEC0 Bit 2 BBCO BERTC0 Bit 13 IEOF Change in BERTEC0 Bit 0 SYNC BERTC0 Bit 15 IESYNC Port I/F # 0 TCOFA TP0CR Bit #14 Port I/F # 0

PDF Datasheet Preview

DS3134 Chateau Channelized T1 And

E1 And HDLC Controller
• 256 Channel HDLC Controller that Supports up to 64 T1 or E1 Lines or Two T3 Lines
• 256 Independent bi-directional HDLC channels
• 16 physical ports 16 Tx & 16 Rx that can be configured as either channelized or unchannelized
• Two fast 52 Mbps ports/other ports capable of speeds up to 10 Mbps unchannelized
• Channelized Ports 0 to 15 handle one, two or four T1 or E1 lines
• Supports up to 64 T1 or E1 data streams
• Per channel DS0 loopbacks in both direction
• Support transparent Mode
• V.54 loopback code detector
• Onboard Bit Error Rate Tester BERT with
auto error insertion capability
• BERT function can be assigned to any HDLC channel or any port
• 104 Mbps full duplex throughput
• Large 16 kbits FIFO in both receive and
transmit directions
• Efficient scatter / gather DMA
• Receive data packets are Time stamped
• Transmit packet priority setting
• Local bus allows for PCI bridging or local
access
• Intel or Motorola bus signals supported
• 25 MHz to 33 MHz 32-bit PCI V2.1
backplane interface
• 3.3V low power CMOS with 5V tolerant I/O
• JTAG support IEEE
• 256 Lead Plastic BGA 27 mm x 27 mm

The DS3134 Chateau device is a 256-channel HDLC controller. The DS3134 is capable of handling up to 64 T1 or E1 data streams or 2 T3 data streams. Each of the 16 physical ports can handle one, two or four T1 or E1 data streams. The Chateau consists of the following blocks
• Layer Block
• HDLC Block
• FIFO Block
• DMA Block
• PCI Bus
• Local Bus
1 of 203
101600

DS3134 There are 16 HDLC Engines one for each port that are capable of operating at speeds up to Mbps in channelized mode and up to 10 Mbps in unchannelized mode. There are also two Fast HDLC Engines, which only reside on Ports 0 and 1 and they are capable of operating at speeds up to 52 Mbps. Applications/Markets include:
• Channelized T1/E1
• Clear channel unchannelized T1/E1
• Channelized T3/E3
• Dual clear channel unchannelized T3/E3
• High density Frame Relay access
• xDSL each port can support up to 10 Mbps
• Dual HSSI
• V.35
• SONET/SDH EOC/ECC Termination
• Any applications require large number of HDLC channels The device fully meets the following specifications ANSI American National Standards Institute T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995 and PCI Local Bus Specification V2.1 June 1, ITU Q.921 March 1993 and ISO Standard 3309-1979 Data Communications HDLC Procedures Frame Structure.
2 of 203

DS3134

Version 1/30/98 Original release.

Version 2 4/4/98 Assigned signals to leads Section Added more information to Sections 1, 5, 7, and Removed the P3VEN signal pin Section and Added FIFO Priority Control bits to the MC register Section Added Abort and Bit Stuffing Control bits to the RHCD and THCD registers Section Changed the Absolute Maximum Voltage Rating and IOH numbers Section Changed the Low Water Mark definition Section Added Section 14 on Applications.

Version 3 6/22/98 Corrected JTRST* lead from V19 to U19 Section Added TEST lead at C3 Section Added the Valid Receive Done Queue Descriptor bit Section Corrected JTAG Device Code from 0000614Ch to 00006143h Section Changed the order of the TABTE & TZSD bits in the THCD Register Section Added JTAG Scan Control Information into Table 11.4A Section Added Minimum Grant & Maximum Latency Settings to PINTL0 Section Remove the HDLC channel restriction that required channels 1 to 128 to be assigned to ports 0 to 7
and HDLC channels 129 to 256 to be assigned to port 8 to 15 Sections 1, and

Version 4 11/18/98 Added information about queues full and empty states Sections and Changed BERT ones and zeros detector from 32 consecutive to 31 consecutive Section Changed BERT Bit and Error Counters to count during loss of receive synchronization Section Corrected Table 1E Section Added bit numbers to register descriptions. Changed Local Bus Configuration Mode AC Timing Parameter A7 from 5ns to 40ns. Section

Version 5 09/01/99 Typos corrections and add clarifications. Section Change the number of T1/E1 support from 64 to 56 due to design over sight Section 1 Added clarifications for Receive High Water Mark and corrected Transmit Low Water Mark to a
value from 1 to smaller or equal to N where N = the number of linked blocks. Removed bit 1 of the RDMAQ register, this function is automatically implemented. Please refer to
section page 90 Figure 10.3A signal LRD* is moved back one LCLK cycle to align with the rising edge of LCLK Figure 103B signal LWR* is moved back one LCLK cycle to align with the rising edge of LCLC
3 of 203
4 of 203

TABLE OF CONTENTS

DS3134

Section 1:

Section 2 Signal 16 Overview / Signal Lead 16 Serial Port Interface Signal 22 Local Bus Signal 24 JTAG Signal 27 PCI Bus Signal 28 Supply & Test Signal 31

Section 3 Memory 32 General Configuration 32 Receive Port 33 Transmit Port 33 Channelized Port 34 HDLC 35 BERT 35 Receive DMA 35 Transmit DMA 36 FIFO 36 PCI Configuration Registers for Function 36 PCI Configuration Registers for Function 37

Section 4 General Device Configuration & 37 Master Reset & ID Register 37 Master Configuration Register 38 Status & 40 Status & Interrupt General 40 Status & Interrupt Register 43 Test Register 50

Section 5 Layer 51 General 51 Port Register 55 Layer One Configuration Register 59 Receive V.54 65 BERT Register 70

Section 6 77 General 77 HDLC Register 79
5 of 203

DS3134 Section 7 85
Bit 6 / PCI Bus Orientation PBO . This bit selects whether HDLC packet data on the PCI Bus will operate in either Little Endian format or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest address while Big Endian places the least significant byte at the highest address. This bit setting only affects HDLC data on the PCI Bus. All other PCI Bus transactions to the internal device configuration registers, PCI configuration registers, and Local Bus, are always in Little Endian format.
0 = HDLC Packet Data on the PCI Bus is in Little Endian format 1 = HDLC Packet Data on the PCI Bus is in Big Endian format
40 of 203

DS3134 Bits 7 to 11 / BERT Port Select Bits 0 to 4 BPS0 to BPS4 . These 5 bits select which port has the dedicated resources of the BERT.
= Port 0 00001 = Port 1 00010 = Port 2 00011 = Port 3 00100 = Port 4 00101 = Port 5 00110 = Port 6 00111 = Port 7
01000 = Port 8 01001 = Port 9 01010 = Port 10 01011 = Port 11 01100 = Port 12 01101 = Port 13 01110 = Port 14 01111 = Port 15
10000 = Port 0 hi speed 10001 = Port 1 hi speed 10010 = n/a 10011 = n/a 10100 = n/a 10101 = n/a 10110 = n/a 10111 = n/a
11000 = n/a 11001 = n/a 11010 = n/a 11011 = n/a 11100 = n/a 11101 = n/a 11110 = n/a = n/a

Bit 12 / Receive FIFO Priority Control Bit 0 RFPC0 .

Bit 13 / Receive FIFO Priority Control Bit 1 RFPC1 . These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest priority to the DMA to transfer data from the FIFO to the PCI Bus. In the priority decoded scheme, the lower the HDLC channel numbers, the higher the priority.
00 = all HDLC channels are serviced Round Robin 01 = HDLC Channels 1 & 2 are Priority Decoded other HDLC Channels are Round Robin 10 = HDLC Channels 1 to 16 are Priority Decoded other HDLC Channels are Round Robin 11 = HDLC Channels 1 to 64 are Priority Decoded other HDLC Channels are Round Robin

Bit 14 / Transmit FIFO Priority Control Bit 0 TFPC0 .

Bit 15 / Transmit FIFO Priority Control Bit 1 TFPC1 . These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest priority to the DMA to transfer data from the PCI Bus to the FIFO. In the priority decoded scheme, the lower the HDLC channel numbers, the higher the priority.
00 = all HDLC channels are serviced Round Robin 01 = HDLC Channels 1 & 2 are Priority Decoded other HDLC Channels are Round Robin 10 = HDLC Channels 1 to 16 are Priority Decoded other HDLC Channels are Round Robin 11 = HDLC Channels 1 to 64 are Priority Decoded other HDLC Channels are Round Robin

STATUS & INTERRUPT

Status & Interrupt General Description of Operation

There are three status register in the device, Status Master SM , Status for the Receive V54 Loopback Detector SV54 , and Status for DMA SDMA . All three registers report events in real time as they occur by setting a bit within the register to a one. All bits that have been set within the register are cleared when the register is read and the bit will not be set again until the event has occurred again. Each bit has the ability to generate an interrupt at the PCI Bus via the PINTA* output signal pin and if the Local Bus is in the Configuration Mode, then an interrupt will also be created at the LINT* output signal pin. Each status register has an associated Interrupt Mask Register, which can allow/deny interrupts from being generated on a bit-by-bit basis. All status remains active even if the associated Interrupt is disabled.
41 of 203

DS3134

SM Register

The Status Master SM register reports events that occur at the Port Interface, at the BERT receiver, at the PCI Bus and at the Local Bus. See Figure 4.3.1A for details.

The Port Interface reports Change Of Frame Alignment COFA events. If the software detects that one of these bits as being set, the software must then begin polling the RP[n]CR or TP[n]CR registers of each active port a maximum of 16 reads to determine which port or ports has incurred a COFA. Also via the Interrupt Enable for Receive COFA IERC and Interrupt Enable for Transmit COFA IETC control bits in the RP[n]CR and TP[n]CR registers respectively, the Host can allow/deny the COFA indications to be passed on to the SRCOFA and STCOFA status bits.

The BERT receiver will report three events, a change in the receive synchronizer status, a bit error being detected, and if either the Bit Counter or the Error Counter overflows. Each of these events can be masked within the BERT function via the BERT Control Register BERTC0 . If the software detects that the BERT has reported an event has occurred, then the software must read the BERT Status Register BERTEC0 to determine which event s has occurred.

The SM register also reports events as they occur in the PCI Bus and the Local Bus. There are no control bits to stop these events from being reported in the SM register. When the Local Bus is operated in the PCI Bridge Mode, SM reports any interrupts detected via the Local Bus LINT* input signal pin and if any timing errors occur because of the use of the external timing signal LRDY*. When the Local Bus is operated in the Configuration Mode, the LBINT and LBE bits are meaningless and should be ignored.

SV54 Register

The Status for Receive V.54 Detector SV54 register reports if the V.54 loopback detector has either timed out in its search for the V.54 loop up pattern or if the detector has found and verified the loop up/down pattern. There is a separate status bit SLBP for each port. When set, the Host must read the VTO and VLB status bits in the RP[n]CR register of the corresponding port to find the exact state of the V.54 detector. When the V.54 detector experiences a time out in it's search for the loop up code VTO = 1 , then the SLBP status bit will be continuously set until the V.54 detector is reset by the Host toggling the VRST bit in RP[n]CR register. There are no control bits to stop these events from being reported in the SV54 register. See Figure 4.3.1A for details on the status bits and Section 5 for details on the operation of the V.54 loopback detector.

SDMA Register

The Status for DMA SDMA register reports events that occur regarding the Receive and Transmit DMA blocks as well as the receive HDLC controller and FIFO. The SDMA will report when the DMA reads from either the Receive Free Queue or Transmit Pending Queue or writes to the Receive or Transmit Done Queues. Also reported are error conditions that might occur in the access of one of these queues. The SDMA will report if any of the HDLC channels experiences a FIFO overflow/underflow condition and if the receive HDLC controller encounters a CRC error, abort signal, or octet length problem on any of the HDLC channels. The Host can determine which specific HDLC channel incurred a FIFO overflow/underflow, CRC error, octet length error or abort by reading the status bits as reported in Done Queues which are created by the DMA. There are no control bits to stop these events from being reported in the SDMA register.
42 of 203

DS3134

STATUS REGISTER BLOCK DIAGRAM FOR SM & SV54 Figure 4.3.1A

BERT

Transmit

Receive

BERTEC0 Bit 1 BECO BERTEC0 Bit 2 BBCO

BERTC0 Bit 13 IEOF

Change in BERTEC0 Bit 0 SYNC

BERTC0 Bit 15 IESYNC

Port I/F # 0

TCOFA TP0CR Bit #14

Port I/F # 0

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DS3134DK Datasheet file may be downloaded here without warranties.

Datasheet ID: DS3134DK 647181