DS1742-70

DS1742-70 Datasheet

DS1742 Y2KC Nonvolatile Timekeeping

Part	Datasheet
DS1742-70	DS1742-70 (pdf)

Related Parts	Information
DS1742-70+	DS1742-70+

PDF Datasheet Preview
DS1742 Y2KC Nonvolatile Timekeeping Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM These Registers are Resident in the Eight Top RAM Locations Century Byte Register Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to the year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for ±10% VCC Power Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness until Power is Applied for the First Time Standard JEDEC Bytewide 2k x 8 Static RAM Pinout Quartz Accuracy ±1 Minute a Month at +25°C, Factory Calibrated UL Recognized PIN CONFIGURATION TOP VIEW A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND DS1742 23 22 VCC A8 A9 WE OE A10 CE ENCAPSULATED DIP ORDERING INFORMATION PART VOLTAGE V TEMP RANGE DS1742-70 DS1742-70+ DS1742-100 DS1742-100+ DS1742-100IND DS1742-100IND+ DS1742W-120 DS1742W-120+ DS1742W-150 DS1742W-150+ DS1742P-100+ 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C +Denotes a lead-free/RoHS-compliant device. DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required must be ordered separately . * The top mark will include a “+” on lead-free devices. PowerCap is a registered trademark of Dallas Semiconductor. PIN-PACKAGE 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 34 TOP MARK** DS1742-070 DS1742+070 DS1742-100 DS1742+100 DS1742-100 IND DS1742+100 IND DS1742W-120 DS1742W+120 DS1742W-150 DS1742W+150 DS1742P+100 1 of 15 DS1742 PIN DESCRIPTION NAME FUNCTION Address Input Data Input/Output Ground Active-Low Chip-Enable Input Active-Low Output-Enable Input Active-Low Write-Enable Input Power-Supply Input The DS1742 is a full-function, year 2000-compliant Y2KC , real-time clock/calendar RTC and 2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide interface as shown in Figure The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1742 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. 2 of 15 DS1742 CLOCK THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1742 registers are updated simultaneously after the internal clock register updating process has been re-enabled. Updating is within a second after the read bit is written to The READ bit must be a zero for a minimum of 500ms to ensure the external registers will be updated. Figure DS1742 BLOCK DIAGRAM Table TRUTH TABLE VCC > VPF VSO < VCC < VPF VCC < VSO < VPF CE OE WE VIH X VIL X VIL VIH VIL VIH XX X XX X MODE Deselect Write Read Deselect

PDF Datasheet Preview

DS1742 Y2KC Nonvolatile Timekeeping

Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM These Registers are Resident in the Eight Top RAM Locations Century Byte Register Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to the year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for ±10% VCC Power Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness until Power is Applied for the First Time Standard JEDEC Bytewide 2k x 8 Static RAM Pinout Quartz Accuracy ±1 Minute a Month at +25°C, Factory Calibrated UL Recognized

PIN CONFIGURATION

TOP VIEW

A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND

DS1742
23 22

VCC A8

A9 WE OE

A10 CE

ENCAPSULATED DIP
ORDERING INFORMATION

PART

VOLTAGE V TEMP RANGE

DS1742-70 DS1742-70+ DS1742-100 DS1742-100+ DS1742-100IND DS1742-100IND+ DS1742W-120 DS1742W-120+ DS1742W-150 DS1742W-150+ DS1742P-100+
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
+Denotes a lead-free/RoHS-compliant device. *DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required must be ordered separately . ** The top mark will include a “+” on lead-free devices. PowerCap is a registered trademark of Dallas Semiconductor.

PIN-PACKAGE 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 24 EDIP 0.740a 34

TOP MARK** DS1742-070 DS1742+070 DS1742-100 DS1742+100 DS1742-100 IND DS1742+100 IND DS1742W-120 DS1742W+120 DS1742W-150 DS1742W+150 DS1742P+100
1 of 15

DS1742

PIN DESCRIPTION

NAME

FUNCTION

Address Input

Data Input/Output

Ground Active-Low Chip-Enable Input Active-Low Output-Enable Input Active-Low Write-Enable Input Power-Supply Input

The DS1742 is a full-function, year 2000-compliant Y2KC , real-time clock/calendar RTC and 2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide interface as shown in Figure The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically.

The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1742 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
2 of 15

DS1742

CLOCK THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1742 registers are updated simultaneously after the internal clock register updating process has been re-enabled. Updating is within a second after the read bit is written to The READ bit must be a zero for a minimum of 500ms to ensure the external registers will be updated.

Figure DS1742 BLOCK DIAGRAM

Table TRUTH TABLE

VCC > VPF

VSO < VCC < VPF VCC < VSO < VPF

CE OE WE

VIH X VIL X VIL VIH VIL VIH XX X XX X

MODE

Deselect Write Read

Deselect

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Datasheet ID: DS1742-70 647162