MX25R6435FM1IL0

MX25R6435FM1IL0 Datasheet

MX25R6435F

Part	Datasheet
MX25R6435FM1IL0	MX25R6435FM1IL0 (pdf)

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MX25R6435F MX25R6435F ULTRA LOW POWER, 64M-BIT [x 1/x 2/x 4] CMOS SERIAL MULTI I/O FLASH MEMORY Key Features • Ultra Low Power Mode and High Performance Mode • Wide Range VCC 1.65V-3.6V for Read, Erase and Program Operations • Unique ID and Secure OTP Support • Multi I/O Support - Single I/O, Dual I/O and Quad I/O • Program Suspend/Resume & Erase Suspend/Resume P/N PM2138 MX25R6435F Contents 4 GENERAL 6 Table Additional PIN CONFIGURATIONS 8 PIN 8 BLOCK 9 DATA 10 Table Protected Area 11 Table 8K-bit Secured OTP MEMORY 13 Table Memory DEVICE 14 HOLD 16 COMMAND 17 Table Command Write Enable 20 Write Disable 21 Read Identification 22 Read Electronic Signature 23 Read Electronic Manufacturer ID & Device ID 24 ID 25 Table ID Definitions Read Status Register 26 Read Configuration Register 27 Write Status Register 32 Table Protection Read Data Bytes 36 Read Data Bytes at Higher Speed 37 Dual Read Mode 38 2 x I/O Read Mode 39 Quad Read Mode 40 4 x I/O Read Mode 41 Burst 43 Performance Enhance 44 Sector Erase 46 Block Erase 47 Block Erase 48 Chip Erase 49 Page Program 50 4 x I/O Page Program 51 Deep Power-down 52 Enter Secured OTP 53 P/N PM2138 MX25R6435F Exit Secured OTP 53 Read Security Register 53 Table Security Register Write Security Register 54 Program Suspend and Erase 55 P/N PM2138 MX25R6435F Ultra Low Power 64M-BIT [x 1/x 2/x 4] CMOS SERIAL MULTI I/O FLASH MEMORY GENERAL • Supports Serial Peripheral Interface -- Mode 0 and Mode 3 • 67,108,864 x 1 bit structure or 33,554,432 x 2 bits two I/O mode structure or 16,777,216 x 4 bits four I/O mode structure • Equal Sectors with 4K byte each or Equal Blocks with 32K/64K byte each - Any Block can be erased individually • Single Power Supply Operation - Operation Voltage 1.65V-3.6V for Read, Erase and Program Operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast read - 1 I/O 80MHz with 8 dummy cycles - 2 I/O 80MHz with 4 dummy cycles, equivalent to 160MHz - 4 I/O 80MHz with 2+4 dummy cycles, equivalent to 320MHz - Fast program and erase time - 8/16/32/64 byte Wrap-Around Burst Read Mode • Ultra Low Power Consumption • Minimum 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions • Additional 8K bits secured OTP - Features unique identifier. - Factory locked identifiable and customer lockable • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths Any page to be programed should have page in the erased state first • Status Register Feature • Command Reset • Program/Erase Suspend and Program/Erase Resume • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameters SFDP mode • Support Unique ID Please contact local Macronix sales for detail information P/N PM2138 MX25R6435F HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • RESET#/SIO3 * or HOLD#/SIO3 * - Hardware Reset pin or Serial input & Output for 4 x I/O read mode or - HOLD feature, to pause the device without deselecting the device or Serial input & Output for 4 x I/O read mode * Depends on part number options • PACKAGE - 8-pin SOP 200mil - 8-land WSON 6x5mm - 8-land USON 4x4mm - 22-ball WLCSP 3-2-3 Ball Array - All devices are RoHS Compliant and Halogen-free P/N PM2138 MX25R6435F MX25R6435F is 64Mb bits Serial NOR Flash memory, which is configured as 8,388,608 x 8 internally. When it is in four I/O mode, the structure becomes 16,777,216 bits x 4 or 33,554,432 bits x MX25R6435F feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input SCLK , a serial data input SI , and a serial data output SO . Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and RESET#/HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25R6435F Serial Multi I/O provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page 256 bytes basis, or word basis for erase command is executed on sector 4K-byte or block 32K-byte , or block 64K-byte , or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. L/H switch bit The Low Power / High Performance bit is a volatile bit. User can change the value of L/H switch bit to keep Ultra Low Power mode or High Performance mode. Please check Ordering Information for the L/H Switch default support. Configuration Register - 1 bit7 bit6 bit5 Reserved bit4 Reserved bit3 TB top/bottom selected 0=Top area protect 1=Bottom area protect Default=0 bit2 Reserved bit1 Reserved bit0 Reserved Configuration Register - 2 bit7 bit6 Reserved bit5 Reserved bit4 Reserved bit3 Reserved bit2 Reserved bit1 L/H Switch 0 = Ultra Low power mode 1 = High performance mode Volatile bit bit0 Reserved P/N PM2138 MX25R6435F Write Status Register WRSR The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before sending WRSR instruction, the Write Enable WREN instruction must be decoded and executed to set the Write Enable Latch WEL bit in advance. The WRSR instruction can change the value of Block Protect BP3, BP2, BP1, BP0 bits to define the protected area of memory as shown in "Table Protected Area Sizes" . The WRSR also can set or reset the Quad enable QE bit and set or reset the Status Register Write Disable SRWD bit in accordance with Write Protection WP#/SIO2 pin signal, but has no effect on bit1 WEL and bit0 WIP of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode HPM is entered. The sequence of issuing WRSR instruction is CS# goes sending WRSR instruction Status Register data on goes high. The CS# must go high exactly at the 8 bits, 16 bits or 24 bits data boundary otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time tW is initiated as soon as Chip Select CS# goes high. The Write in Progress WIP bit still can be checked during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch WEL bit is reset. Please note that there is another parameter, "Write Status Register cycle time for Mode Changing Switching tWMS ", which is only for the self-timed of Mode Switching changing L/H switch bit . For more detail please check "Table AC Characteristics". Figure Write Status Register WRSR Sequence CS# Mode 3 SCLK Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 command 01h High-Z Status Register In Configuration Register -1 In ORDERING INFORMATION Voltage MX25R6435FM2IL0 1.65V-3.6V Package 8-SOP 200mil Temperature RESET# / HOLD# pin Default Mode -40°C to 85°C RESET# Ultra Low Power Mode MX25R6435FZNIL0 1.65V-3.6V 8-WSON 6x5mm -40°C to 85°C RESET# Ultra Low Power Mode MX25R6435FZAIL0 1.65V-3.6V 8-USON 4x4mm -40°C to 85°C RESET# Ultra Low Power Mode MX25R6435FBDIL0 1.65V-3.6V 3-2-3 22-BALL WLCSP -40°C to 85°C RESET# Ultra Low Power Mode MX25R6435FM2IH0 1.65V-3.6V 8-SOP 200mil -40°C to 85°C RESET# High Performance Mode MX25R6435FZAIH0 1.65V-3.6V 8-USON 4x4mm -40°C to 85°C RESET# High Performance Mode P/N PM2138 MX25R6435F PART NAME DESCRIPTION MX 25R 6435F M2 I L 0 OPTION 2 0 RESET# 1 HOLD# OPTION 1 L Ultra Low Power Mode Default H High Performance Mode Default TEMPERATURE RANGE I Industrial -40°C to 85°C PACKAGE M2 8-SOP 200mil ZN 8-WSON ZA 8-USON 4x4mm BD 22-Ball WLCSP DENSITY & MODE 6435F 64Mb DEVICE 25R Wide Range VCC Serial NOR Flash 1.65V-3.6V P/N PM2138 PACKAGE INFORMATION MX25R6435F P/N PM2138 MX25R6435F P/N PM2138 MX25R6435F P/N PM2138 MX25R6435F SO/SIO1 RESET#/SIO3* SI/SIO0 WP#/SIO2 SCLK * RESET#/SIO3 or HOLD#/SIO3 Depends on part number options Please contact local Macronix sales channel for complete package dimensions. P/N PM2138 MX25R6435F Modified Voltage in Feature page Updated the ORDERING INFORMATION content. Added description of 32K byte block JAN/30/2015 Modified WLCSP package description P83,84 Added WLCSP package information Updated parameters for DC/AC Characteristics Updated Erase and Programming Performance P8,88 P71-76 P81 MAR/19/2015 Added 2.3V~3.6V and 1.65V~2.0V option MAY/18/2015 Added HOLD# option Updated parameters for DC/AC Characteristics P67,68,70 Removed L/H Switch bit descriptions default value Updated 1 I/O and 2 I/O High Performance Mode Frequency. P4,7,67,70 Added Notice at Performance Enhance Mode P/N PM2138 MX25R6435F Removed "Preliminary" to align with the product status Modified REMS description Added "Figure High Voltage Operation Diagram" Removed tRES2 Modified VWI 2.3V-3.6V option Modified ISB1 Ultra Low Power Mode Optimized typical tPRS/tERS values and descriptions Added MX25R6435FZAIHV Part No. Updated Erase/Program Cycle value definition Removed Performance Enhance Mode Reset Page All P24 P52 P60 P23,68,70 P74 P66 P69,71 P77 P4,75 Date SEP/04/2015 Removed 2.3V-3.6V and 1.65V-2.0V option SEP/18/2015 Added MX25R6435FM2IH0 & MX25R6435FZAIH0 Part No. Content modification OCT/16/2015 P30,40,68,70, P/N PM2138 MX25R6435F Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright Macronix International Co., Ltd. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich io, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto if any are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at:

PDF Datasheet Preview

MX25R6435F

MX25R6435F

ULTRA LOW POWER, 64M-BIT [x 1/x 2/x 4] CMOS SERIAL MULTI I/O FLASH MEMORY

Key Features
• Ultra Low Power Mode and High Performance Mode
• Wide Range VCC 1.65V-3.6V for Read, Erase and Program Operations
• Unique ID and Secure OTP Support
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Program Suspend/Resume & Erase Suspend/Resume

P/N PM2138

MX25R6435F

Contents
4 GENERAL 6

Table Additional PIN CONFIGURATIONS 8 PIN 8 BLOCK 9 DATA 10

Table Protected Area 11 Table 8K-bit Secured OTP MEMORY 13 Table Memory DEVICE 14 HOLD 16 COMMAND 17 Table Command Write Enable 20 Write Disable 21 Read Identification 22 Read Electronic Signature 23 Read Electronic Manufacturer ID & Device ID 24 ID 25 Table ID Definitions Read Status Register 26 Read Configuration Register 27 Write Status Register 32 Table Protection Read Data Bytes 36 Read Data Bytes at Higher Speed 37 Dual Read Mode 38 2 x I/O Read Mode 39 Quad Read Mode 40 4 x I/O Read Mode 41 Burst 43 Performance Enhance 44 Sector Erase 46 Block Erase 47 Block Erase 48 Chip Erase 49 Page Program 50 4 x I/O Page Program 51 Deep Power-down 52 Enter Secured OTP 53

P/N PM2138

MX25R6435F

Exit Secured OTP 53 Read Security Register 53

Table Security Register Write Security Register 54 Program Suspend and Erase 55
P/N PM2138

MX25R6435F

Ultra Low Power 64M-BIT [x 1/x 2/x 4] CMOS SERIAL MULTI I/O FLASH MEMORY

GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 67,108,864 x 1 bit structure or 33,554,432 x 2 bits two I/O mode structure or 16,777,216 x 4 bits four I/O
mode structure
• Equal Sectors with 4K byte each or Equal Blocks with 32K/64K byte each - Any Block can be erased individually
• Single Power Supply Operation - Operation Voltage 1.65V-3.6V for Read, Erase and Program Operations
• Latch-up protected to 100mA from -1V to Vcc +1V

PERFORMANCE
• High Performance
- Fast read - 1 I/O 80MHz with 8 dummy cycles - 2 I/O 80MHz with 4 dummy cycles, equivalent to 160MHz - 4 I/O 80MHz with 2+4 dummy cycles, equivalent to 320MHz
- Fast program and erase time - 8/16/32/64 byte Wrap-Around Burst Read Mode
• Ultra Low Power Consumption
• Minimum 100,000 erase/program cycles
• 20 years data retention

SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
• Additional 8K bits secured OTP
- Features unique identifier.
- Factory locked identifiable and customer lockable
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths Any page to be programed should have page in the erased state first
• Status Register Feature
• Command Reset
• Program/Erase Suspend and Program/Erase Resume
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters SFDP mode
• Support Unique ID Please contact local Macronix sales for detail information

P/N PM2138

MX25R6435F

HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• RESET#/SIO3 * or HOLD#/SIO3 *
- Hardware Reset pin or Serial input & Output for 4 x I/O read mode or
- HOLD feature, to pause the device without deselecting the device or Serial input & Output for 4 x I/O read mode * Depends on part number options
• PACKAGE - 8-pin SOP 200mil
- 8-land WSON 6x5mm - 8-land USON 4x4mm - 22-ball WLCSP 3-2-3 Ball Array
- All devices are RoHS Compliant and Halogen-free

P/N PM2138

MX25R6435F

MX25R6435F is 64Mb bits Serial NOR Flash memory, which is configured as 8,388,608 x 8 internally. When it is in four I/O mode, the structure becomes 16,777,216 bits x 4 or 33,554,432 bits x MX25R6435F feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input SCLK , a serial data input SI , and a serial data output SO . Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and RESET#/HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25R6435F Serial Multi I/O provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page 256 bytes basis, or word basis for erase command is executed on sector 4K-byte or block 32K-byte , or block 64K-byte , or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.
L/H switch bit The Low Power / High Performance bit is a volatile bit. User can change the value of L/H switch bit to keep Ultra Low Power mode or High Performance mode. Please check Ordering Information for the L/H Switch default support.

Configuration Register - 1
bit7
bit6
bit5

Reserved
bit4 Reserved
bit3 TB top/bottom selected
0=Top area protect
1=Bottom area protect Default=0
bit2 Reserved
bit1 Reserved
bit0 Reserved

Configuration Register - 2
bit7
bit6

Reserved
bit5 Reserved
bit4 Reserved
bit3 Reserved
bit2 Reserved
bit1 L/H Switch
0 = Ultra Low power mode
1 = High performance
mode

Volatile bit
bit0 Reserved

P/N PM2138

MX25R6435F

Write Status Register WRSR

The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before sending WRSR instruction, the Write Enable WREN instruction must be decoded and executed to set the Write Enable Latch WEL bit in advance. The WRSR instruction can change the value of Block Protect BP3, BP2, BP1, BP0 bits to define the protected area of memory as shown in "Table Protected Area Sizes" . The WRSR also can set or reset the Quad enable QE bit and set or reset the Status Register Write Disable SRWD bit in accordance with Write Protection WP#/SIO2 pin signal, but has no effect on bit1 WEL and bit0 WIP of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode HPM is entered.

The sequence of issuing WRSR instruction is CS# goes sending WRSR instruction Status Register data on goes high.

The CS# must go high exactly at the 8 bits, 16 bits or 24 bits data boundary otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time tW is initiated as soon as Chip Select CS# goes high. The Write in Progress WIP bit still can be checked during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch WEL bit is reset. Please note that there is another parameter, "Write Status Register cycle time for Mode Changing Switching tWMS ", which is only for the self-timed of Mode Switching changing L/H switch bit . For more detail please check "Table AC Characteristics".

Figure Write Status Register WRSR Sequence

CS# Mode 3

SCLK Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
command 01h

High-Z

Status Register In

Configuration Register -1 In
ORDERING INFORMATION

Voltage

MX25R6435FM2IL0 1.65V-3.6V

Package 8-SOP 200mil

Temperature

RESET# / HOLD# pin

Default Mode
-40°C to 85°C RESET# Ultra Low Power Mode

MX25R6435FZNIL0 1.65V-3.6V 8-WSON 6x5mm -40°C to 85°C RESET# Ultra Low Power Mode

MX25R6435FZAIL0 1.65V-3.6V 8-USON 4x4mm -40°C to 85°C RESET# Ultra Low Power Mode

MX25R6435FBDIL0 1.65V-3.6V 3-2-3 22-BALL WLCSP -40°C to 85°C RESET# Ultra Low Power Mode

MX25R6435FM2IH0 1.65V-3.6V 8-SOP 200mil
-40°C to 85°C RESET# High Performance Mode

MX25R6435FZAIH0 1.65V-3.6V 8-USON 4x4mm -40°C to 85°C RESET# High Performance Mode

P/N PM2138

MX25R6435F

PART NAME DESCRIPTION MX 25R 6435F M2 I L 0

OPTION 2 0 RESET#
1 HOLD#

OPTION 1 L Ultra Low Power Mode Default

H High Performance Mode Default

TEMPERATURE RANGE I Industrial -40°C to 85°C

PACKAGE M2 8-SOP 200mil ZN 8-WSON ZA 8-USON 4x4mm BD 22-Ball WLCSP

DENSITY & MODE 6435F 64Mb

DEVICE 25R Wide Range VCC Serial NOR Flash 1.65V-3.6V

P/N PM2138

PACKAGE INFORMATION

MX25R6435F

P/N PM2138

MX25R6435F

P/N PM2138

MX25R6435F

P/N PM2138

MX25R6435F

SO/SIO1 RESET#/SIO3* SI/SIO0

WP#/SIO2 SCLK
* RESET#/SIO3 or HOLD#/SIO3 Depends on part number options

Please contact local Macronix sales channel for complete package dimensions.

P/N PM2138

MX25R6435F

Modified Voltage in Feature page
Updated the ORDERING INFORMATION content.

Added description of 32K byte block

JAN/30/2015

Modified WLCSP package description

P83,84

Added WLCSP package information

Updated parameters for DC/AC Characteristics

Updated Erase and Programming Performance

P8,88 P71-76 P81

MAR/19/2015

Added 2.3V~3.6V and 1.65V~2.0V option

MAY/18/2015

Added HOLD# option

Updated parameters for DC/AC Characteristics

P67,68,70

Removed L/H Switch bit descriptions default value

Updated 1 I/O and 2 I/O High Performance Mode Frequency. P4,7,67,70

Added Notice at Performance Enhance Mode

P/N PM2138

MX25R6435F

Removed "Preliminary" to align with the product status

Modified REMS description

Added "Figure High Voltage Operation Diagram"

Removed tRES2

Modified VWI 2.3V-3.6V option

Modified ISB1 Ultra Low Power Mode

Optimized typical tPRS/tERS values and descriptions

Added MX25R6435FZAIHV Part No.

Updated Erase/Program Cycle value definition

Removed Performance Enhance Mode Reset

Page All P24 P52 P60 P23,68,70 P74 P66 P69,71 P77 P4,75

Date SEP/04/2015

Removed 2.3V-3.6V and 1.65V-2.0V option

SEP/18/2015

Added MX25R6435FM2IH0 & MX25R6435FZAIH0 Part No.

Content modification

OCT/16/2015

P30,40,68,70,

P/N PM2138

MX25R6435F

Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright Macronix International Co., Ltd. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich io, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto if any are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at:

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Datasheet ID: MX25R6435FM1IL0 646944