SP725AATG

SP725AATG Datasheet


Lead-Free/Green SP725

Part Datasheet
SP725AATG SP725AATG SP725AATG (pdf)
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Lead-Free/Green SP725

TVS Diode Arrays Devices

General Purpose ESD Protection - SP725 Series

SP725 Series 5pF 8kV Diode Array

RoHS Pb GREEN

Pinout

In 1 In 2 In 3 In 4

SP725AB T G SOIC
8 V7 V6 V+ 5 V+

In 1 In 2 In 3 In 4 NC 5

SP725AATG MSOP-10L
10 V9 V8 V+ 7 V+ 6 NC

Functional Block Diagram

V+ 5, 6

IN 3, 4

V7, 8

The SP725 is an array of SCR/Diode bipolar structures for ESD and overvoltage protection of sensitive input circuits. The SP725 has 2 protection SCR/Diode device structures per input. There are a total of 4 available inputs that can be used to protect up to 4 external signal or bus lines. Overvoltage protection is from the IN Pins 1 - 4 to V+ or V-.

The SCR structures are designed for fast triggering at a threshold of one +VBE diode threshold above V+ Pin 5,6 or one diode threshold below V- Pin From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one VBE above V+. A similar clamp to V- is activated if a negative pulse, one VBE less than V-, is applied to an IN input.

Refer to Fig 1 and Table 1 for further details. Refer to Application Note AN9304 and AN9612 for further detail.
• ESD Interface per HBM Standards - IEC 61000-4-2, Direct Discharge........... 8kV Level 4 - IEC 61000-4-2, Air Discharge................15kV Level 4 -
• Peak Current Capability - IEC 61000-4-5 8/20 µs Peak Pulse Current........ ± 9 A - Single Transient Pulse, 100 µs Pulse Width....... ± 4 A
• Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to......................... +30V - Differential Voltage Range to............................. ±15V
• Fast Risetime
• Low Input Leakages...........................5 nA at 25 ºC Typical
• Low Input pF Typical
• An Array of 4 SCR/Diode Pairs
• Operating Temperature Range..................-40 ºC to 105 ºC
• Microprocessor/Logic Input Protection
• Data Bus Protection
• Analog Device Input Protection
• Voltage Clamp

Life Support Note Not Intended for Use in Life Support or Life Saving Applications The products shown herein are not designed for use in life sustaining or life saving applications unless otherwise expressly indicated.
2012 Littelfuse, Inc. Specifications are subject to change without notice. Please refer to for current information.

SP725 Lead-Free/Green Series

TVS Diode Arrays Devices

General Purpose ESD Protection - SP725 Series

Absolute Maximum Ratings

Thermal Information

Parameter Continuous Supply Voltage, V+ - V- Forward Peak Current, IIN to VCC , IIN to GND

Rating +35
± 4, 100 µs ±9

Units V A

CAUTION Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Parameter Thermal Resistance Typical, Note 1

SOIC Package Storage Temperature Range Maximum Junction Temperature Maximum Lead Temperature Soldering 20-40s SOIC - Lead Tips Only

Rating 170
-65 to 150

Units oC/W oC/W
Ordering Information

Part Number SP725AATG SP725ABG SP725ABTG

Temp. Range ºC -40 to 105 -40 to 105 -40 to 105

Package

Marking

MSOP-10L

LF725A
8 Ld SOIC

SP725AB T G 1
8 Ld SOIC Tape and Reel SP725AB T G 1

Min. Order Qty. 4000 1960 2500

Notes SP725AB T G means device marking either SP725ABG or SP725ABTG.
2012 Littelfuse, Inc. Specifications are subject to change without notice. Please refer to for current information.

SP725 Lead-Free/Green Series

TVS Diode Arrays Devices

General Purpose ESD Protection - SP725 Series

Package Dimensions Small Outline Plastic Packages SOIC

INDEX AREA

Package Pins

JEDEC

SEATING PLANE
h x 45o

M C A M B S

Symbols are defined in the “MO Series Symbol List” in Section of Publication

Number

Dimensioning and tolerancing per ANSI Y14.5M-1982.

Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm inch per side.

Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm inch per side.

The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
“L” is the length of terminal for soldering to a substrate.
“N” is the number of terminal positions.

Terminal numbers are shown for reference only.

The lead width “B”, as measured 0.36mm inch or greater above the seating plane, shall not exceed a maximum value of 0.61mm inch .

Controlling dimension MILLIMETER. Converted inch dimensions are not necessarily exact.

Embossed Carrier Tape & Reel - SOIC Package

User Feeding Direction Pin 1 Location

E F P2 D D1 P0 10P0 W P A0 B0 K0 t

Millimeters

SOIC

MS-012
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Datasheet ID: SP725AATG 646559