LFXP10C-H-EV
LFXP10C-H-EV Datasheet
The LatticeXP is manufactured to operate with multiple 1.2V to 5V voltage ranges. The LFXP10E device requires a core voltage supply at 1.2V and an auxiliary I/O supply at 3.3V. The LFXP10C device requires a core voltage supply at 1.5V-3.3V, and an auxiliary 3.3V supply. The LatticeXP Advanced Evaluation Board provides four supply voltages, all sourced from a 5V external source. The board provides fixed 1.2V, 2.5V and 3.3V power rails, and a single adjustable voltage that ranges from 1.2V to 3.3V. It is possible to use external power supplies to override the fixed output levels, if it is required. The voltage supplied to the LatticeXP core is selectable using shunts.
| Part | Datasheet |
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LFXP10C-H-EV |
LFXP10C-H-EV (pdf) |
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| LatticeXP Advanced Evaluation Board User’s Guide Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Introduction Traditional SRAM-based FPGA solutions require additional non-volatile memory components be placed onto the printed circuit board PCB , consuming additional resources and adding cost to the PCB solution. Alternatives to the SRAM-based FPGA include fuse based FPGAs or ASIC devices. While these solutions provide a non-volatile solution, they cannot be re-programmed. The LatticeXP is a non-volatile, re-programmable FPGA solution, including both SRAM-based FPGA cells for easy reconfiguration and Flash-based memory for non-volatility, all in one efficient package. The LatticeXP Advanced Evaluation Board is designed to help the user examine key features of the LatticeXP device and to aid in the development of custom designs. It is a ready-made, proven platform that includes a variety of industry-standard memory and communication interfaces. • Single board solution for evaluation of the LatticeXP FPGA • LatticeXP FPGA in a 388-ball fpBGA package • DDR SODIMM socket and DDR power generation • FCRAM interface and memory • 10/100/1000 Mbps Ethernet PHY to an RJ45 connector • PCI plated finger connections • Seven-segment LED • Eight LEDs for visual feedback • Eight-position switch input • JTAG programming/boundary scan interface • Built-in power supply operating from 5V external supply AC adapter included • Selectable CORE voltage for the LatticeXP • Selectable voltages for all eight I/O banks • Built in oscillator for reference clocks • SMA connectors to LatticeXP clock input and general purpose I/O pins • 100mil center-center test point grid The heart of the LatticeXP Advanced Evaluation board is the LatticeXP FPGA. Around this core device are several industry standard interfaces and protocol devices. The LatticeXP is manufactured to operate with multiple 1.2V to 5V voltage ranges. The LFXP10E device requires a core voltage supply at 1.2V and an auxiliary I/O supply at 3.3V. The LFXP10C device requires a core voltage supply at 1.5V-3.3V, and an auxiliary 3.3V supply. The LatticeXP Advanced Evaluation Board provides four supply voltages, all sourced from a 5V external source. The board provides fixed 1.2V, 2.5V and 3.3V power rails, and a single adjustable voltage that ranges from 1.2V to 3.3V. It is possible to use external power supplies to override the fixed output levels, if it is required. The voltage supplied to the LatticeXP core is selectable using shunts. Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Once a correct set of supply voltages has been applied to the LatticeXP FPGA, the device is ready for programming. The LatticeXP FPGA is typically programmed and verified from the JTAG interface. A JTAG download cable can be connected onto either a 1x10 SIP header or a 2x5 DIP header. The LatticeXP is typically programmed using the Lattice System software. The ispVM System software can be downloaded from the Lattice web site at ispVM System or later should be used to program the LatticeXP device. The ispVM System software can be used to program either the SRAM memory or the Flash cells. The internal Flash memory on the LatticeXP device can be reprogrammed in the background while the FPGA is operating. LatticeXP devices can also be programmed using either serial or parallel interfaces. The parallel interface permits either the SRAM or the Flash PROM memories to be programmed in the same manner as the JTAG port. The slave serial and master serial modes available on the LatticeXP only program the SRAM memory. The LatticeXP Advanced board does not support these alternate programming modes directly. Test points are provided on the board for connecting to the serial programming points. The parallel programming interface is inaccessible since it is connected to provide the FCRAM memory function. Once programmed, the LatticeXP device has access to several interfaces designed to highlight FPGA features. The LatticeXP directly interfaces to a set of switches, LEDs, a seven segment display, a prototype grid, a FCRAM chip, Double-data-rate DRAM, a set of SMA connectors, a PCI bus and an Ethernet PHY device. One of the key interfaces supported directly in the LatticeXP FPGA is easy support for DDR DRAM memories. The evaluation board provides a DDR SODIMM socket for inserting SODIMM DDR modules. The LatticeXP directly controls the address and memory strobes and connects to a 16-bit data bus. The data bus requires data qualification strobes DQS also be present. The LatticeXP FPGA series has an internal hardware assist for managing the DQS signals. These signals are connected to the DDR SODIMM. The DDR interface is capable of running at 167MHz 333 DDR . The FCRAM interface also uses the LatticeXP DQS hardware assist. The LatticeXP Advanced Evaluation board provides a single FCRAM device, providing an eight-bit data bus. Data rates to between the FCRAM and the LatticeXP are equivalent to the DDR interface. The evaluation board also provides a 3.3V 33MHz, 32-bit PCI interface. The board is designed to only be inserted into 3.3V PCI backplanes. It is not recommended to install the board into a 5V backplane. The LatticeXP FPGA is not directly 5V tolerant. In order for the device to be placed into a 5V system the PCI I/O clamp diodes must be enabled, and series current limiting resistors need to be on each 5V I/O. The evaluation board includes a 10/100/1000 Ethernet PHY device National Semiconductor DP83865 . All of the necessary support components are provided to connect to a 10/100/1000 Base-T network. The physical side of the PHY connects to an RJ45 connector with built-in isolation magnetics and a 3KV capacitor. The Media Independent Interface MII is connected to the LatticeXP FPGA. The LatticeXP must be programmed with a Media Access Controller MAC before Ethernet traffic can be routed across the interface. Additional features of the LatticeXP Advanced Evaluation board are described in detail in the following section. Additional Resources Additional resources related to this board can be downloaded from the web at Click on the appropriate evaluation board, then see the blue “Resources” box on the right of the screen for items such as updated documentation, software, sample designs, IP evaluation bitstreams, and more. LatticeXP Advanced Evaluation Board Functional Description The LatticeXP Advanced Evaluation Board is comprised of several primary functional blocks as shown in Figure In the descriptions below, locations of components and board features will be described relative to a compass symbol placed adjacent to the Lattice logo. For example, the seven-segment LED is on the northwest corner of the board, and the trimmer potentiometer is on the southeast corner of the board. Lattice Semiconductor LatticeXP Advanced Evaluation Board User’s Guide Figure LatticeXP Advanced Evaluation Board Functional Blocks Seven-Segment LEDs and SMT LEDs Prototype Grid FCRAM Chip Center Pins Connectors Program/Reset Center Pins Switches Configuration Switch DIP Switches 5V/GND Posts RJ45 Connector DC Input Jack Ethernet PHY Ordering Information Description LatticeXP10C Evaluation Board - Advanced LatticeXP Advanced Evaluation Board User’s Guide China RoHS Environment-Friendly Ordering Part Number Use Period EFUP LFXP10C-H-EV Technical Support Assistance Hotline 1-800-LATTICE North America +1-503-268-8001 Outside North America e-mail Internet: Date July 2005 March 2007 April 2007 September 2009 Version Change Summary Initial release. Added Ordering Information section. Added important information for proper connection of ispDOWNLOAD Programming Cables. 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Lattice Semiconductor Appendix A. Schematics LatticeXP Advanced Evaluation Board User’s Guide D [6] TP_AB2 [6] TP_W 8 [8] VCC_3.3V VCC_3.3V R85 10K CR0402 PCI_INTA_N PCI_INTC_N PCI_INTD_N AB2 PCI_REQ_N AA3 PCI_GNT_N AB3 PCI_RST_N PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_INTB_N PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_SERR_N AB9 PCI_LOCK_N AA9 PCI_PERR_N W10 PCI_PAR PCI_DEVSEL_NAB10 PCI_AD17 AA10 PCI_STOP_N AA11 PCI_FRAME_N AB11 P CI_ IRDY_N Y11 P C I_TRDY_N Y12 BANK 5 BANK 4 LFXP10C fpBGA388 2 OF 5 |
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