OR3T556BA256-DB

OR3T556BA256-DB Datasheet

OR3C80 OR3T20

Part	Datasheet
OR3T556BA256-DB	OR3T556BA256-DB (pdf)

Related Parts	Information
OR3T307S208-DB	OR3T307S208-DB
OR3T306S208I-DB	OR3T306S208I-DB
OR3T557S208-DB	OR3T557S208-DB
OR3T557BA256-DB	OR3T557BA256-DB
OR3T556S208I-DB	OR3T556S208I-DB
OR3T556S208-DB	OR3T556S208-DB
OR3T307BA256-DB	OR3T307BA256-DB
OR3T306S208-DB	OR3T306S208-DB
OR3T306BA256I-DB	OR3T306BA256I-DB
OR3T306BA256-DB	OR3T306BA256-DB
OR3T556BA256I-DB	OR3T556BA256I-DB

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ORCA Series 3C and 3T FPGA Device Datasheet June 2010 Select Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line OR3C80 OR3T20 OR3T30 OR3T55 Ordering Part Number OR3C805PS208-DB OR3C804PS208-DB OR3C804PS208I-DB OR3C804BA352-DB OR3T206T144-DB OR3T207S208-DB OR3T206S208-DB OR3T206S208I-DB OR3T207BA256-DB OR3T206BA256-DB OR3T307S208-DB OR3T306S208-DB OR3T306S208I-DB OR3T307S240-DB OR3T306S240-DB OR3T306S240I-DB OR3T307BA256-DB OR3T306BA256-DB OR3T306BA256I-DB OR3T557S208-DB OR3T556S208-DB OR3T556S208I-DB OR3T557PS240-DB OR3T556PS240-DB OR3T556PS240I-DB Product Status Discontinued Reference PCN PCN#02-06 Discontinued PCN#09-10 Active / Orderable Discontinued Active / Orderable Active / Orderable Discontinued PCN#12A-09 PCN#06-07 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone 503 268-8000 z FAX 503 268-8347 Internet: Product Line OR3T55 Cont’d OR3T80 OR3T125 Ordering Part Number OR3T557BA256-DB OR3T556BA256-DB OR3T556BA256I-DB OR3T557BA352-DB OR3T556BA352-DB OR3T556BA352I-DB OR3T807S208-DB OR3T806S208-DB OR3T806S208I-DB OR3T807PS240-DB OR3T806PS240-DB OR3T806PS240I-DB OR3T807BA352-DB OR3T806BA352-DB OR3T806BA352I-DB OR3T807BC432-DB OR3T806BC432-DB OR3T806BC432I-DB OR3T1257PS208-DB OR3T1256PS208-DB OR3T1256PS208I-DB OR3T1257PS240-DB OR3T1256PS240-DB OR3T1256PS240I-DB OR3T1257BA352-DB OR3T1256BA352-DB OR3T1256BA352I-DB OR3T1257BC432-DB OR3T1256BC432-DB OR3T1256BC432I-DB Product Status Active / Orderable Reference PCN Discontinued PCN#09-10 Discontinued PCN#09-10 Discontinued PCN#06-07 Discontinued PCN#09-10 Discontinued PCN#06-07 PCN#09-10 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone 503 268-8000 z FAX 503 268-8347 Internet: Data Sheet November 2006 Field-ProOgRrCamAmSaebrleiSeGs a3tCe aAnrdra3yTs Features E • High-performance, cost-effective, µm OR3C and µm OR3T 4-level metal technology, 4- or 5-input look-up table delay of ns with -7 speed grade in IC µm . • Same basic architecture as lower-voltage, advanced D process technology Series 3 architectures. See ORCA Series 3L FPGA documentation. V • Up to 186,000 usable gates. E • Up to 342 user I/Os. OR3Txxx I/Os are 5 V tolerant to allow interconnection to both V and 5 V devices, selectable on a per-pin basis. E U • Pin selectable I/O clamping diodes provide 5 V or V PCI compliance and 5 V tolerance on OR3Txxx devices. • Twin-quad programmable function unit PFU architec- D ture with eight 16-bit look-up tables LUTs per PFU, IN organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. • Nine user registers per PFU, one following each LUT, T plus one extra. All have programmable clock enable and local set/reset, plus a global set/reset that can be disabled per PFU. C • Flexible input structure FINS of the PFUs provides a N routability enhancement for LUTs with shared inputs and the logic of LUTs with independent inputs. • Fast-carry logic and routing to adjacent PFUs for nibble-, E byte-wide, or longer arithmetic functions, with the option O to register the PFU carry-out. • Softwired LUTs SWL allow fast cascading of up to L three levels of LUT logic in a single PFU for up to 40% speed improvement. E C • Supplemental logic and interconnect cell SLIC provides 3-statable buffers, up to 10-bit decoder, and PALlike AND-OR with optional INVERT in each programma- ble logic cell PLC , with over 50% speed improvement typical. SELDEICSTCODNETVIINCUEED Ordering Lattice Semiconductor ORCA Series 3C and 3T FPGAs Data Sheet November 2006 System-Level Features phase and duty cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be combined with System-level features reduce glue logic requirements FPGA logic to create complex functions, such as dig- and make a system on a chip possible. These features ital phase-locked loops DPLL , frequency counters, in the ORCA Series 3 include: and frequency synthesizers or clock doublers. Two PCMs are provided per device. • Full PCI local bus compliance. • Dual-use microprocessor interface MPI can be used for readback, device control, and S device status, as well as for a general-purpose inter- face to the FPGA. Glueless interface to i960 and PowerPC† processors with E address space provided. • Parallel readback of data capability with the built-in microprocessor interface. IC • Programmable clock manager PCM adjusts clock • True, internal, 3-state, bidirectional buses with simple control provided by the SLIC. • 32 x 4 RAM per PFU, as single- or dualport at >176 MHz. Create large, fast RAM/ROM blocks 128 x 8 in only eight PFUs using the SLIC decoders as bank drivers. * i960 is a registered trademark of Intel Corporation. † PowerPC is a registered trademark of International Business Machines Corporation. D Table ORCA Series 3 System Performance V E Parameter E 16-bit Loadable Up/Down Counter U 16-bit Accumulator 8 x 8 Parallel Multiplier: D Multiplier Mode, Unpipelined1 IN ROM Mode, Unpipelined2 Multiplier Mode, Pipelined3 32 x 16 RAM synchronous : T Single-port, 3-state Bus4 T Dual-port5 128 x 8 RAM synchronous : C Single-port, 3-state Bus4 N Dual-port5 8-bit Address Decode internal : E Using Softwired LUTs O Using SLICs6 32-bit Address Decode internal : L Using Softwired LUTs E C Using SLICs7 36-bit Parity Check internal # PFUs Speed 78 102 131 168 designation see Ordering Information uses a single- junction temperature is in the Package Thermal digit number to designate a speed grade. This number is not related to any single ac parameter. Higher numbers indicate a faster set of timing parameters. The S actual speed sorting is based on testing the delay in a path consisting of an input buffer, combinatorial delay through all PLCs in a row, and an output buffer. Other E tests are then done to verify other delay parameters, such as routing delays, setup times to FFs, etc. The most accurate timing characteristics are reported IC by the timing analyzer in the ispLEVER Development D System. A timing report provided by the development system after layout divides path delays into logic and routing delays. The timing analyzer can also provide V E logic delays prior to layout. While this allows routing budget estimates, there is wide variance in routing delays associated with different layouts. E U The logic timing parameters noted in the Electrical Characteristics section of this data sheet are the same D as those in the design tools. In the PFU timing given in Table 48, symbol names are generally a concatenation of the PFU operating mode as in Table 3 and the parameter type. The setup, hold, T and propagation delay parameters, below, are T designated in the symbol name by the SET, HLD, and DEL characters, respectively. C N The values given for the parameters are the same as those used during production testing and speed bin- E ning of the devices. The junction temperature and supO ply voltage used to characterize the devices are listed in the delay tables. Actual delays at nominal tempera- L ture and voltage for best-case processes can be much better than the values given. E C It should be noted that the junction temperature used in the tables is generally 85 °C. The junction temperature S IS for the FPGA depends on the power dissipated by the device, the package thermal characteristics ΘJA , and the ambient temperature, as calculated in the following equation and as discussed further in the Package D Thermal Characteristics section: Characteristics section. Taken cumulatively, the range of parameter values for best-case vs. worst-case processing, supply voltage, and junction temperature can approach 3 to Table Derating for Commercial Devices OR3Cxx Power Supply Voltage Table Derating for Industrial Devices OR3Cxx 0 25 85 100 125 Power Supply Voltage Table Derating for Commercial/Industrial Devices OR3Txxx 0 25 85 100 125 Power Supply Voltage Note The derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. Since the Ordering Information OR3XXXX X XX XXX X XX Device Family Packing Designator OR3T20 DB = Dry Packed Tray OR3T30 OR3T55 OR3C80 OR3T80 S OR3T125 E Speed Grade VIC ED Table Ordering Information E U Device Family D OR3C80 T TIN OR3T20 SELDEICSCON OR3T30 OR3C805PS208-DB2 OR3C805BA352-DB2 OR3C804PS208-DB2 OR3C804BA352-DB2 OR3T207S208-DB OR3T207BA256-DB OR3T206S208-DB OR3T206T144-DB OR3T206BA256-DB OR3T307S208-DB OR3T307S240-DB OR3T307BA256-DB OR3T306S208-DB OR3T306S240-DB OR3T306BA256-DB Grade Blank = Commercial I = Industrial Pin/Ball Count Package Type BA = Plastic Ball Grid Array PBGA BC = Enhanced Ball Grid Array EBGA PS = Power Quad Shrink Flat Package SQFP2 S = Shrink Quad Flat Package SQFP T = Thin Quad Flat Package TQFP Commercial Speed Grade 5 4 7 6 7 6 Package Type SQFP2 PBGA SQFP2 PBGA SQFP PBGA SQFP TQFP PBGA SQFP PBGA SQFP PBGA Pin/Ball Count 208 352 208 352 208 256 208 144 256 208 240 256 208 240 256 Grade Packing Designator Lattice Semiconductor ORCA Series 3C and 3T FPGAs Data Sheet November 2006 Commercial Device Family Speed Grade Package Type Pin/Ball Count Grade Packing Designator OR3T55 OR3T557PS208-DB1 SQFP2 ICES OR3T80 SELDEICSTCODNETVINUED OR3T125 OR3T557S208-DB OR3T557PS240-DB3 OR3T557BA256-DB OR3T557BA352-DB OR3T556PS208-DB1 OR3T556S208-DB OR3T556PS240-DB3 OR3T556BA256-DB OR3T556BA352-DB OR3T807PS208-DB1 OR3T807S208-DB OR3T807PS240-DB3 OR3T807BA352-DB OR3T807BC432-DB OR3T806PS208-DB1 OR3T806S208-DB OR3T806PS240-DB3 OR3T806BA352-DB OR3T806BC432-DB OR3T1257PS208-DB3 OR3T1257PS240-DB3 OR3T1257BA352-DB OR3T1257BC432-DB OR3T1256PS208-DB3 OR3T1256PS240-DB3 OR3T1256BA352-DB OR3T1256BC432-DB SQFP SQFP2 PBGA PBGA SQFP2 SQFP SQFP2 PBGA PBGA SQFP2

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ORCA Series 3C and 3T FPGA Device Datasheet

June 2010

Select Devices Discontinued!

Product Change Notifications PCNs have been issued to discontinue select devices in this data sheet.

The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status.

Product Line

OR3C80 OR3T20

OR3T30

OR3T55
Ordering Part Number

OR3C805PS208-DB OR3C804PS208-DB OR3C804PS208I-DB OR3C804BA352-DB OR3T206T144-DB OR3T207S208-DB OR3T206S208-DB OR3T206S208I-DB OR3T207BA256-DB OR3T206BA256-DB OR3T307S208-DB OR3T306S208-DB OR3T306S208I-DB OR3T307S240-DB OR3T306S240-DB OR3T306S240I-DB OR3T307BA256-DB OR3T306BA256-DB OR3T306BA256I-DB OR3T557S208-DB OR3T556S208-DB OR3T556S208I-DB OR3T557PS240-DB OR3T556PS240-DB OR3T556PS240I-DB

Product Status

Discontinued

Reference PCN

PCN#02-06

Discontinued

PCN#09-10

Active / Orderable Discontinued

Active / Orderable Active / Orderable

Discontinued

PCN#12A-09 PCN#06-07
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone 503 268-8000 z FAX 503 268-8347 Internet:

Product Line

OR3T55 Cont’d

OR3T80

OR3T125
Ordering Part Number

OR3T557BA256-DB OR3T556BA256-DB OR3T556BA256I-DB OR3T557BA352-DB OR3T556BA352-DB OR3T556BA352I-DB OR3T807S208-DB OR3T806S208-DB OR3T806S208I-DB OR3T807PS240-DB OR3T806PS240-DB OR3T806PS240I-DB OR3T807BA352-DB OR3T806BA352-DB OR3T806BA352I-DB OR3T807BC432-DB OR3T806BC432-DB OR3T806BC432I-DB OR3T1257PS208-DB OR3T1256PS208-DB OR3T1256PS208I-DB OR3T1257PS240-DB OR3T1256PS240-DB OR3T1256PS240I-DB OR3T1257BA352-DB OR3T1256BA352-DB OR3T1256BA352I-DB OR3T1257BC432-DB OR3T1256BC432-DB OR3T1256BC432I-DB

Product Status

Active / Orderable

Reference PCN

Discontinued

PCN#09-10

Discontinued

PCN#09-10

Discontinued

PCN#06-07

Discontinued

PCN#09-10

Discontinued

PCN#06-07 PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone 503 268-8000 z FAX 503 268-8347 Internet:

Data Sheet November 2006

Field-ProOgRrCamAmSaebrleiSeGs a3tCe aAnrdra3yTs Features E
• High-performance, cost-effective, µm OR3C and
µm OR3T 4-level metal technology, 4- or 5-input look-up table delay of ns with -7 speed grade in

IC µm .
• Same basic architecture as lower-voltage, advanced

D process technology Series 3 architectures. See ORCA

Series 3L FPGA documentation.

V
• Up to 186,000 usable gates. E
• Up to 342 user I/Os. OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both V and 5 V devices, selectable on a per-pin basis.

E U
• Pin selectable I/O clamping diodes provide 5 V or V PCI compliance and 5 V tolerance on OR3Txxx devices.
• Twin-quad programmable function unit PFU architec-

D ture with eight 16-bit look-up tables LUTs per PFU, IN organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions in a single PFU.
• Nine user registers per PFU, one following each LUT,

T plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be disabled per PFU.

C
• Flexible input structure FINS of the PFUs provides a N routability enhancement for LUTs with shared inputs and
the logic of LUTs with independent inputs.
• Fast-carry logic and routing to adjacent PFUs for nibble-,

E byte-wide, or longer arithmetic functions, with the option O to register the PFU carry-out.
• Softwired LUTs SWL allow fast cascading of up to

L three levels of LUT logic in a single PFU for up to 40%
speed improvement.

E C
• Supplemental logic and interconnect cell SLIC provides 3-statable buffers, up to 10-bit decoder, and PAL*like AND-OR with optional INVERT in each programma-
ble logic cell PLC , with over 50% speed improvement typical.
SELDEICSTCODNETVIINCUEED Ordering

Lattice Semiconductor

ORCA Series 3C and 3T FPGAs

Data Sheet November 2006

System-Level Features
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with

System-level features reduce glue logic requirements

FPGA logic to create complex functions, such as dig-
and make a system on a chip possible. These features
ital phase-locked loops DPLL , frequency counters,
in the ORCA Series 3 include:
and frequency synthesizers or clock doublers. Two

PCMs are provided per device.
• Full PCI local bus compliance.
• Dual-use microprocessor interface MPI can be used for readback, device control, and

S device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960 * and PowerPC† processors with

E address space provided.
• Parallel readback of data capability with the built-in microprocessor interface.

IC
• Programmable clock manager PCM adjusts clock
• True, internal, 3-state, bidirectional buses with simple control provided by the SLIC.
• 32 x 4 RAM per PFU, as single- or dualport at >176 MHz. Create large, fast RAM/ROM blocks 128 x 8 in only eight PFUs using the SLIC decoders as bank drivers.
* i960 is a registered trademark of Intel Corporation. † PowerPC is a registered trademark of International Business

Machines Corporation.

D Table ORCA Series 3 System Performance

V E Parameter E 16-bit Loadable Up/Down Counter U 16-bit Accumulator
8 x 8 Parallel Multiplier:

D Multiplier Mode, Unpipelined1 IN ROM Mode, Unpipelined2

Multiplier Mode, Pipelined3 32 x 16 RAM synchronous :

T Single-port, 3-state Bus4 T Dual-port5
128 x 8 RAM synchronous :

C Single-port, 3-state Bus4 N Dual-port5
8-bit Address Decode internal :

E Using Softwired LUTs O Using SLICs6
32-bit Address Decode internal :

L Using Softwired LUTs E C Using SLICs7
36-bit Parity Check internal
# PFUs

Speed
78 102 131 168
designation see Ordering Information uses a single-
junction temperature is in the Package Thermal
digit number to designate a speed grade. This number is not related to any single ac parameter. Higher numbers indicate a faster set of timing parameters. The

S actual speed sorting is based on testing the delay in a
path consisting of an input buffer, combinatorial delay through all PLCs in a row, and an output buffer. Other

E tests are then done to verify other delay parameters,
such as routing delays, setup times to FFs, etc.

The most accurate timing characteristics are reported

IC by the timing analyzer in the ispLEVER Development D System. A timing report provided by the development
system after layout divides path delays into logic and routing delays. The timing analyzer can also provide

V E logic delays prior to layout. While this allows routing
budget estimates, there is wide variance in routing delays associated with different layouts.

E U The logic timing parameters noted in the Electrical

Characteristics section of this data sheet are the same

D as those in the design tools. In the PFU timing given in Table 48, symbol names are generally a
concatenation of the PFU operating mode as in Table 3 and the parameter type. The setup, hold,

T and propagation delay parameters, below, are T designated in the symbol name by the SET, HLD, and

DEL characters, respectively.

C N The values given for the parameters are the same as
those used during production testing and speed bin-

E ning of the devices. The junction temperature and supO ply voltage used to characterize the devices are listed
in the delay tables. Actual delays at nominal tempera-

L ture and voltage for best-case processes can be much
better than the values given.

E C It should be noted that the junction temperature used in
the tables is generally 85 °C. The junction temperature

S IS for the FPGA depends on the power dissipated by the
device, the package thermal characteristics ΘJA , and the ambient temperature, as calculated in the following equation and as discussed further in the Package

D Thermal Characteristics section:

Characteristics section. Taken cumulatively, the range of parameter values for best-case vs. worst-case processing, supply voltage, and junction temperature can approach 3 to

Table Derating for Commercial Devices OR3Cxx

Power Supply Voltage

Table Derating for Industrial Devices OR3Cxx
0 25 85
100 125

Power Supply Voltage

Table Derating for Commercial/Industrial Devices OR3Txxx
0 25 85
100 125

Power Supply Voltage

Note The derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. Since the
Ordering Information

OR3XXXX X XX XXX X XX

Device Family

Packing Designator

OR3T20

DB = Dry Packed Tray

OR3T30 OR3T55 OR3C80 OR3T80

S OR3T125 E Speed Grade
VIC ED Table Ordering Information

E U Device Family

D OR3C80 T TIN OR3T20 SELDEICSCON OR3T30

OR3C805PS208-DB2 OR3C805BA352-DB2 OR3C804PS208-DB2 OR3C804BA352-DB2 OR3T207S208-DB OR3T207BA256-DB OR3T206S208-DB OR3T206T144-DB OR3T206BA256-DB OR3T307S208-DB OR3T307S240-DB OR3T307BA256-DB OR3T306S208-DB OR3T306S240-DB OR3T306BA256-DB

Grade Blank = Commercial I = Industrial

Pin/Ball Count

Package Type BA = Plastic Ball Grid Array PBGA BC = Enhanced Ball Grid Array EBGA PS = Power Quad Shrink Flat Package SQFP2 S = Shrink Quad Flat Package SQFP T = Thin Quad Flat Package TQFP

Commercial

Speed Grade
5 4 7 6 7 6

Package Type

SQFP2 PBGA SQFP2 PBGA SQFP PBGA SQFP TQFP PBGA SQFP PBGA SQFP PBGA

Pin/Ball Count
208 352 208 352 208 256 208 144 256 208 240 256 208 240 256

Grade

Packing Designator

Lattice Semiconductor

ORCA Series 3C and 3T FPGAs

Data Sheet November 2006

Commercial

Device Family

Speed Grade

Package Type

Pin/Ball Count

Grade

Packing Designator

OR3T55

OR3T557PS208-DB1

SQFP2

ICES OR3T80 SELDEICSTCODNETVINUED OR3T125

OR3T557S208-DB OR3T557PS240-DB3 OR3T557BA256-DB OR3T557BA352-DB OR3T556PS208-DB1 OR3T556S208-DB OR3T556PS240-DB3 OR3T556BA256-DB OR3T556BA352-DB OR3T807PS208-DB1 OR3T807S208-DB OR3T807PS240-DB3 OR3T807BA352-DB OR3T807BC432-DB OR3T806PS208-DB1 OR3T806S208-DB OR3T806PS240-DB3 OR3T806BA352-DB OR3T806BC432-DB OR3T1257PS208-DB3 OR3T1257PS240-DB3 OR3T1257BA352-DB OR3T1257BC432-DB OR3T1256PS208-DB3 OR3T1256PS240-DB3 OR3T1256BA352-DB OR3T1256BC432-DB

SQFP

SQFP2

PBGA

PBGA

SQFP2

SQFP

SQFP2

PBGA

PBGA

SQFP2

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Datasheet ID: OR3T556BA256-DB 645493