M5LV-384/120-10YC
M5LV-384/120-10YC Datasheet
M5-128/1 M5LV-128
| Part | Datasheet |
|---|---|
M5LV-384/120-10YC |
M5LV-384/120-10YC (pdf) |
| Related Parts | Information |
|---|---|
|
M5LV-128/120-12YC |
M5LV-128/120-12YC |
|
M5LV-128/68-10VI |
M5LV-128/68-10VI |
|
M5LV-128/68-10VC |
M5LV-128/68-10VC |
|
M5LV-128/120-7YI |
M5LV-128/120-7YI |
|
M5-320/160-7YC |
M5-320/160-7YC |
|
M5LV-128/120-7YC |
M5LV-128/120-7YC |
|
M5LV-128/120-5YC |
M5LV-128/120-5YC |
|
M5LV-128/68-12VC |
M5LV-128/68-12VC |
|
M5LV-128/120-12YI |
M5LV-128/120-12YI |
|
M5-320/192-7SAI |
M5-320/192-7SAI |
|
M5LV-128/120-10YI |
M5LV-128/120-10YI |
|
M5LV-128/120-10YC |
M5LV-128/120-10YC |
|
M5LV-128/104-7VI |
M5LV-128/104-7VI |
|
M5LV-128/104-7VC |
M5LV-128/104-7VC |
|
M5-384/160-10YI |
M5-384/160-10YI |
|
M5LV-128/120-15YI |
M5LV-128/120-15YI |
|
M5-320/192-12SAC |
M5-320/192-12SAC |
|
M5-320/192-7SAC |
M5-320/192-7SAC |
|
M5-320/192-6SAC |
M5-320/192-6SAC |
|
M5-320/192-20SAI |
M5-320/192-20SAI |
|
M5-320/192-15SAI |
M5-320/192-15SAI |
|
M5-512/160-15YC |
M5-512/160-15YC |
|
M5-320/192-15SAC |
M5-320/192-15SAC |
|
M5-384/160-10YC |
M5-384/160-10YC |
|
M5-320/192-12SAI |
M5-320/192-12SAI |
|
M5LV-128/68-12VI |
M5LV-128/68-12VI |
|
M5-320/192-10SAI |
M5-320/192-10SAI |
|
M5-320/192-10SAC |
M5-320/192-10SAC |
|
M5-320/160-7YI |
M5-320/160-7YI |
|
M5LV-128/68-7VC |
M5LV-128/68-7VC |
|
M5LV-128/68-5VC |
M5LV-128/68-5VC |
|
M5LV-128/68-15VI |
M5LV-128/68-15VI |
|
M5-384/160-12YC |
M5-384/160-12YC |
|
M5-512/256-20SAI |
M5-512/256-20SAI |
|
M5LV-128/104-12VI |
M5LV-128/104-12VI |
|
M5-512/160-7YI |
M5-512/160-7YI |
|
M5-512/256-10SAC |
M5-512/256-10SAC |
|
M5-512/256-10SAI |
M5-512/256-10SAI |
|
M5-512/256-12SAC |
M5-512/256-12SAC |
|
M5-512/256-15SAI |
M5-512/256-15SAI |
|
M5-512/160-6YC |
M5-512/160-6YC |
|
M5-512/256-12SAI |
M5-512/256-12SAI |
|
M5LV-128/104-12VC |
M5LV-128/104-12VC |
|
M5-512/256-6SAC |
M5-512/256-6SAC |
|
M5LV-128/104-10VI |
M5LV-128/104-10VI |
|
M5LV-128/104-10VC |
M5LV-128/104-10VC |
|
M5-512/256-7SAI |
M5-512/256-7SAI |
|
M5-320/160-6YC |
M5-320/160-6YC |
|
M5-512/256-7SAC |
M5-512/256-7SAC |
|
M5-512/256-15SAC |
M5-512/256-15SAC |
|
M5-512/160-12YC |
M5-512/160-12YC |
|
M5-384/160-15YC |
M5-384/160-15YC |
|
M5-384/160-15YI |
M5-384/160-15YI |
|
M5-384/160-20YI |
M5-384/160-20YI |
|
M5-384/160-6YC |
M5-384/160-6YC |
|
M5-384/160-7YC |
M5-384/160-7YC |
|
M5-384/160-7YI |
M5-384/160-7YI |
|
M5-512/160-7YC |
M5-512/160-7YC |
|
M5-512/160-10YI |
M5-512/160-10YI |
|
M5-384/160-12YI |
M5-384/160-12YI |
|
M5LV-128/104-5VC |
M5LV-128/104-5VC |
|
M5LV-128/104-15VI |
M5LV-128/104-15VI |
|
M5-512/160-12YI |
M5-512/160-12YI |
|
M5-256/120-12YC/1 |
M5-256/120-12YC/1 |
|
M5-512/160-15YI |
M5-512/160-15YI |
|
M5-512/160-20YI |
M5-512/160-20YI |
|
M5-512/160-10YC |
M5-512/160-10YC |
|
M5-192/120-12YC/1 |
M5-192/120-12YC/1 |
|
M5-128/68-20VI/1 |
M5-128/68-20VI/1 |
M5-128/68-20YI/1 |
M5-128/68-20YI/1 |
|
M5-128/68-5VC/1 |
M5-128/68-5VC/1 |
M5-128/68-5YC/1 |
M5-128/68-5YC/1 |
|
M5-128/68-7VC/1 |
M5-128/68-7VC/1 |
|
M5-128/68-7VI/1 |
M5-128/68-7VI/1 |
M5-128/68-7YC/1 |
M5-128/68-7YC/1 |
M5-128/68-7YI/1 |
M5-128/68-7YI/1 |
|
M5-192/68-10VI/1 |
M5-192/68-10VI/1 |
|
M5-192/120-10YI/1 |
M5-192/120-10YI/1 |
|
M5-128/68-15VI/1 |
M5-128/68-15VI/1 |
|
M5-192/120-12YI/1 |
M5-192/120-12YI/1 |
|
M5-192/120-15YC/1 |
M5-192/120-15YC/1 |
|
M5-192/120-15YI/1 |
M5-192/120-15YI/1 |
|
M5-192/120-20YI/1 |
M5-192/120-20YI/1 |
|
M5-192/120-5YC/1 |
M5-192/120-5YC/1 |
|
M5-192/120-7YC/1 |
M5-192/120-7YC/1 |
|
M5-192/120-7YI/1 |
M5-192/120-7YI/1 |
|
M5-256/120-15YC/1 |
M5-256/120-15YC/1 |
|
M5-192/120-10YC/1 |
M5-192/120-10YC/1 |
|
M5-128/68-10VC/1 |
M5-128/68-10VC/1 |
|
M5-128/120-10YC/1 |
M5-128/120-10YC/1 |
|
M5-128/120-10YI/1 |
M5-128/120-10YI/1 |
|
M5-128/120-12YC/1 |
M5-128/120-12YC/1 |
|
M5-128/120-12YI/1 |
M5-128/120-12YI/1 |
|
M5-128/120-15YC/1 |
M5-128/120-15YC/1 |
|
M5-128/120-15YI/1 |
M5-128/120-15YI/1 |
|
M5-128/120-20YI/1 |
M5-128/120-20YI/1 |
|
M5-128/120-5YC/1 |
M5-128/120-5YC/1 |
M5-128/68-15YI/1 |
M5-128/68-15YI/1 |
|
M5-128/120-7YI/1 |
M5-128/120-7YI/1 |
M5-128/68-15YC/1 |
M5-128/68-15YC/1 |
|
M5-128/68-10VI/1 |
M5-128/68-10VI/1 |
M5-128/68-10YC/1 |
M5-128/68-10YC/1 |
M5-128/68-10YI/1 |
M5-128/68-10YI/1 |
|
M5-128/68-12VC/1 |
M5-128/68-12VC/1 |
|
M5-128/68-12VI/1 |
M5-128/68-12VI/1 |
M5-128/68-12YC/1 |
M5-128/68-12YC/1 |
M5-128/68-12YI/1 |
M5-128/68-12YI/1 |
|
M5-128/68-15VC/1 |
M5-128/68-15VC/1 |
|
M5-192/68-12VC/1 |
M5-192/68-12VC/1 |
|
M5-128/120-7YC/1 |
M5-128/120-7YC/1 |
|
M5-256/68-5VC/1 |
M5-256/68-5VC/1 |
|
M5-256/160-15YI/1 |
M5-256/160-15YI/1 |
|
M5-256/160-20YI/1 |
M5-256/160-20YI/1 |
|
M5-256/160-5YC/1 |
M5-256/160-5YC/1 |
|
M5-256/160-7YC/1 |
M5-256/160-7YC/1 |
|
M5-256/160-7YI/1 |
M5-256/160-7YI/1 |
|
M5-256/68-10VI/1 |
M5-256/68-10VI/1 |
|
M5-256/68-12VI/1 |
M5-256/68-12VI/1 |
|
M5-256/68-15VC/1 |
M5-256/68-15VC/1 |
|
M5-192/68-10VC/1 |
M5-192/68-10VC/1 |
|
M5-256/68-20VI/1 |
M5-256/68-20VI/1 |
|
M5-256/160-12YC/1 |
M5-256/160-12YC/1 |
|
M5-256/68-7VC/1 |
M5-256/68-7VC/1 |
|
M5-256/68-7VI/1 |
M5-256/68-7VI/1 |
|
M5-320/160-10YC |
M5-320/160-10YC |
|
M5-320/160-10YI |
M5-320/160-10YI |
|
M5-320/160-12YC |
M5-320/160-12YC |
|
M5-320/160-12YI |
M5-320/160-12YI |
|
M5-320/160-15YC |
M5-320/160-15YC |
|
M5-320/160-15YI |
M5-320/160-15YI |
|
M5-256/68-15VI/1 |
M5-256/68-15VI/1 |
|
M5-256/120-12YI/1 |
M5-256/120-12YI/1 |
|
M5-192/68-12VI/1 |
M5-192/68-12VI/1 |
|
M5-192/68-15VC/1 |
M5-192/68-15VC/1 |
|
M5-192/68-15VI/1 |
M5-192/68-15VI/1 |
|
M5-192/68-20VI/1 |
M5-192/68-20VI/1 |
|
M5-192/68-5VC/1 |
M5-192/68-5VC/1 |
|
M5-192/68-7VC/1 |
M5-192/68-7VC/1 |
|
M5-192/68-7VI/1 |
M5-192/68-7VI/1 |
|
M5-256/120-10YC/1 |
M5-256/120-10YC/1 |
|
M5-256/160-15YC/1 |
M5-256/160-15YC/1 |
|
M5-256/68-12VC/1 |
M5-256/68-12VC/1 |
|
M5-256/160-12YI/1 |
M5-256/160-12YI/1 |
|
M5LV-128/68-7VI |
M5LV-128/68-7VI |
|
M5-256/120-15YI/1 |
M5-256/120-15YI/1 |
|
M5-256/120-20YI/1 |
M5-256/120-20YI/1 |
|
M5-256/120-5YC/1 |
M5-256/120-5YC/1 |
|
M5-256/120-7YC/1 |
M5-256/120-7YC/1 |
|
M5-256/120-7YI/1 |
M5-256/120-7YI/1 |
|
M5-256/160-10YC/1 |
M5-256/160-10YC/1 |
|
M5-256/160-10YI/1 |
M5-256/160-10YI/1 |
|
M5-320/160-20YI |
M5-320/160-20YI |
|
M5-256/120-10YI/1 |
M5-256/120-10YI/1 |
|
M5LV-384/120-15YC |
M5LV-384/120-15YC |
|
M5LV-384/160-7YC |
M5LV-384/160-7YC |
|
M5LV-384/160-6YC |
M5LV-384/160-6YC |
|
M5LV-384/160-20YI |
M5LV-384/160-20YI |
|
M5LV-384/160-15YI |
M5LV-384/160-15YI |
|
M5LV-384/160-15YC |
M5LV-384/160-15YC |
|
M5LV-384/160-12YI |
M5LV-384/160-12YI |
|
M5LV-384/160-12YC |
M5LV-384/160-12YC |
|
M5LV-384/160-10YI |
M5LV-384/160-10YI |
|
M5LV-384/160-10YC |
M5LV-384/160-10YC |
|
M5LV-384/120-7YI |
M5LV-384/120-7YI |
|
M5LV-384/120-7YC |
M5LV-384/120-7YC |
|
M5LV-384/120-6YC |
M5LV-384/120-6YC |
|
M5LV-320/160-10YC |
M5LV-320/160-10YC |
|
M5LV-384/120-15YI |
M5LV-384/120-15YI |
|
M5LV-512/120-10YI |
M5LV-512/120-10YI |
|
M5LV-384/120-12YI |
M5LV-384/120-12YI |
|
M5LV-384/120-12YC |
M5LV-384/120-12YC |
|
M5LV-384/120-10YI |
M5LV-384/120-10YI |
|
M5LV-320/160-7YI |
M5LV-320/160-7YI |
|
M5LV-320/160-7YC |
M5LV-320/160-7YC |
|
M5LV-320/160-6YC |
M5LV-320/160-6YC |
|
M5LV-320/160-20YI |
M5LV-320/160-20YI |
|
M5LV-320/160-15YI |
M5LV-320/160-15YI |
|
M5LV-320/160-15YC |
M5LV-320/160-15YC |
|
M5LV-320/160-12YI |
M5LV-320/160-12YI |
|
M5LV-320/160-12YC |
M5LV-320/160-12YC |
|
M5LV-320/160-10YI |
M5LV-320/160-10YI |
|
M5LV-384/120-20YI |
M5LV-384/120-20YI |
|
M5LV-512/160-15YC |
M5LV-512/160-15YC |
|
M5-256/68-10VC/1 |
M5-256/68-10VC/1 |
|
M5LV-128/74-10VC |
M5LV-128/74-10VC |
|
M5LV-512/256-7SAI |
M5LV-512/256-7SAI |
|
M5LV-512/256-6SAC |
M5LV-512/256-6SAC |
|
M5LV-512/256-15SAI |
M5LV-512/256-15SAI |
|
M5LV-512/256-15SAC |
M5LV-512/256-15SAC |
|
M5LV-512/256-12SAI |
M5LV-512/256-12SAI |
|
M5LV-512/256-12SAC |
M5LV-512/256-12SAC |
|
M5LV-512/256-10SAI |
M5LV-512/256-10SAI |
|
M5LV-512/256-10SAC |
M5LV-512/256-10SAC |
|
M5LV-512/160-7YI |
M5LV-512/160-7YI |
|
M5LV-512/160-7YC |
M5LV-512/160-7YC |
|
M5LV-512/160-6YC |
M5LV-512/160-6YC |
|
M5LV-384/160-7YI |
M5LV-384/160-7YI |
|
M5LV-512/120-7YC |
M5LV-512/120-7YC |
|
M5LV-512/256-20SAI |
M5LV-512/256-20SAI |
|
M5LV-512/120-12YC |
M5LV-512/120-12YC |
|
M5LV-512/120-12YI |
M5LV-512/120-12YI |
|
M5LV-512/120-15YC |
M5LV-512/120-15YC |
|
M5LV-512/120-15YI |
M5LV-512/120-15YI |
|
M5LV-512/160-20YI |
M5LV-512/160-20YI |
|
M5LV-512/120-6YC |
M5LV-512/120-6YC |
|
M5LV-512/160-15YI |
M5LV-512/160-15YI |
|
M5LV-512/120-7YI |
M5LV-512/120-7YI |
|
M5LV-512/160-10YC |
M5LV-512/160-10YC |
|
M5LV-512/160-10YI |
M5LV-512/160-10YI |
|
M5LV-512/160-12YC |
M5LV-512/160-12YC |
|
M5LV-512/160-12YI |
M5LV-512/160-12YI |
|
M5LV-512/120-10YC |
M5LV-512/120-10YC |
|
M5LV-512/120-20YI |
M5LV-512/120-20YI |
|
M5LV-256/120-10YI |
M5LV-256/120-10YI |
|
M5LV-128/74-7VC |
M5LV-128/74-7VC |
|
M5LV-128/74-12VC |
M5LV-128/74-12VC |
|
M5LV-256/160-5YC |
M5LV-256/160-5YC |
|
M5LV-256/160-15YI |
M5LV-256/160-15YI |
|
M5LV-256/160-12YI |
M5LV-256/160-12YI |
|
M5LV-256/160-12YC |
M5LV-256/160-12YC |
|
M5LV-256/160-10YI |
M5LV-256/160-10YI |
|
M5LV-256/160-10YC |
M5LV-256/160-10YC |
|
M5LV-256/120-7YI |
M5LV-256/120-7YI |
|
M5LV-256/120-7YC |
M5LV-256/120-7YC |
|
M5LV-256/120-5YC |
M5LV-256/120-5YC |
|
M5LV-256/120-15YI |
M5LV-256/120-15YI |
|
M5LV-256/160-7YC |
M5LV-256/160-7YC |
|
M5LV-256/120-12YC |
M5LV-256/120-12YC |
|
M5LV-256/160-7YI |
M5LV-256/160-7YI |
|
M5LV-256/120-10YC |
M5LV-256/120-10YC |
|
M5LV-256/104-7VI |
M5LV-256/104-7VI |
|
M5LV-128/74-12VI |
M5LV-128/74-12VI |
|
M5LV-256/104-7VC |
M5LV-256/104-7VC |
|
M5LV-256/104-5VC |
M5LV-256/104-5VC |
|
M5LV-256/104-15VI |
M5LV-256/104-15VI |
|
M5LV-256/104-12VI |
M5LV-256/104-12VI |
|
M5LV-256/104-12VC |
M5LV-256/104-12VC |
|
M5LV-256/104-10VI |
M5LV-256/104-10VI |
|
M5LV-256/104-10VC |
M5LV-256/104-10VC |
|
M5LV-128/74-5VC |
M5LV-128/74-5VC |
|
M5LV-128/74-7VI |
M5LV-128/74-7VI |
|
M5LV-256/120-12YI |
M5LV-256/120-12YI |
|
M5LV-256/74-5VC |
M5LV-256/74-5VC |
|
M5LV-320/120-7YC |
M5LV-320/120-7YC |
|
M5LV-320/120-6YC |
M5LV-320/120-6YC |
|
M5LV-320/120-20YI |
M5LV-320/120-20YI |
|
M5LV-320/120-15YI |
M5LV-320/120-15YI |
|
M5LV-512/256-7SAC |
M5LV-512/256-7SAC |
|
M5LV-320/120-15YC |
M5LV-320/120-15YC |
|
M5LV-320/120-7YI |
M5LV-320/120-7YI |
|
M5LV-320/120-12YI |
M5LV-320/120-12YI |
|
M5LV-320/120-12YC |
M5LV-320/120-12YC |
|
M5LV-320/120-10YI |
M5LV-320/120-10YI |
|
M5LV-320/120-10YC |
M5LV-320/120-10YC |
|
M5LV-128/74-10VI |
M5LV-128/74-10VI |
|
M5LV-256/74-7VC |
M5LV-256/74-7VC |
M5LV-256/68-7YI |
M5LV-256/68-7YI |
M5LV-256/68-10YC |
M5LV-256/68-10YC |
M5LV-256/68-10YI |
M5LV-256/68-10YI |
M5LV-256/68-12YC |
M5LV-256/68-12YC |
M5LV-256/68-12YI |
M5LV-256/68-12YI |
M5LV-256/68-15YI |
M5LV-256/68-15YI |
|
M5LV-256/74-7VI |
M5LV-256/74-7VI |
M5LV-256/68-7YC |
M5LV-256/68-7YC |
|
M5LV-128/74-15VI |
M5LV-128/74-15VI |
|
M5LV-256/74-10VC |
M5LV-256/74-10VC |
|
M5LV-256/74-10VI |
M5LV-256/74-10VI |
|
M5LV-256/74-12VC |
M5LV-256/74-12VC |
|
M5LV-256/74-12VI |
M5LV-256/74-12VI |
|
M5LV-256/74-15VI |
M5LV-256/74-15VI |
M5LV-256/68-5YC |
M5LV-256/68-5YC |
| PDF Datasheet Preview |
|---|
| Select devices have been discontinued. See Ordering Information section for product status. MACH 5 CPLD Family Fifth Generation MACH Architecture High logic densities and I/Os for increased logic integration 128 to 512 macrocell densities 68 to 256 I/Os Wide selection of density and I/O combinations to support most application needs 6 macrocell density options 7 I/O options Up to 4 I/O options per macrocell density Up to 5 density & I/O options for each package Performance features to system needs ns tPD Commercial, ns tPD Industrial 182 MHz fCNT Four programmable power/speed settings per block Flexible architecture facilitates logic design Multiple levels of switch matrices allow for performance-based routing 100% routability and pin-out retention Synchronous and asynchronous clocking, including dual-edge clocking Asynchronous product- or sum-term set or reset 16 to 64 output enables Functions of up to 32 product terms Advanced capabilities for easy system integration 3.3-V & 5-V JEDEC-compliant operations IEEE compliant for boundary scan testing 3.3-V & 5-V in-system programmable via IEEE Boundary Scan Test Access Port PCI compliant -5/-6/-7/-10/-12 speed grades Safe for mixed supply voltage system design Bus-Friendly Inputs & I/Os Individual output slew rate control Hot socketing Programmable security bit Advanced E2CMOS process provides high performance, cost effective solutions Publication# 20446 Amendment/0 Select devices have been discontinued. See Ordering Information section for product status. Feature Supply Voltage V Macrocells Maximum User I/O Pins tPD ns tSS ns tCOS ns fCNT MHz Typical Static Power mA IEEE Boundary Scan Compliant PCI-Compliant Table MACH 5 Device Features 1 M5-128/1 M5LV-128 M5-192/1 M5-256/1 M5LV-256 M5-320 M5LV-320 256 320 160 192 160 182 167 Note “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices. M5-384 M5LV-384 M5-512 M5LV-512 The 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices CPLDs . The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options Table The MACH 5 family offers 5-V M5-xxx and 3.3-V M5LV-xxx operation. Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as ns Table The 10, and 12ns devices are compliant with the PCI Local Bus Specification. MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. Device M5-1282 M5-128/1 M5LV-128 M5-192/1 M5-2562 M5-256/1 M5LV-256 M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 Table MACH 5 Speed Grades Speed Grade1 Note C = Commercial grade, I = Industrial grade /1 version recommended for new designs With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512 macrocells to support full system logic integration. Extensive routing resources ensure pinout retention as well as high utilization. It is ideal for block device integration and a wide range of other applications including highspeed computing, low-power applications, communications, and embedded control. At each macrocell density point, Lattice offers several I/O and package options to meet a wide range of design needs Table Supply Voltage 100-pin TQFP 100-pin PQFP 144-pin TQFP 144-pin PQFP 160-pin PQFP 208-pin PQFP 240-pin PQFP 256-ball BGA 352-ball BGA Table MACH 5 Package and I/O Options 1 M5-128/1 M5LV-128 M5-192/1 M5-256/1 M5LV-256 M5-320 M5LV-320 68, 74 68*, 74 104* 104* 104* 104* 120* 184* 184* 192* M5-384 M5LV-384 120* 184* 184* 192* 192* M5-512 M5LV-512 120* 184* 184* 192* 192* Note The I/O options indicated with a “*” are obsolete, please contact factory for more information. Advanced power management options allow designers to incrementally reduce power while maintaining the level of performance needed for today’s complex designs. I/O safety features allow for mixed-voltage design, MACH 5 Family and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE Test Access Port TAP interface. FUNCTIONAL DESCRIPTION The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the segments together. The only logic difference between any two MACH 5 devices is the number of segments. Therefore, once a designer is familiar with one device, consistent performance can be expected across the entire family. All devices have four clock pins available which can also be used as logic inputs. CLK Block: 16 MCs Segment 4 Blocks Block Interconnect Select devices have been discontinued. See Ordering Information section for product status. Segment Interconnect Figure MACH 5 Block Diagram 20446G-001 The MACH 5 PAL blocks consist of the elements listed below Figure While each PAL block resembles an independent PAL device, it has superior control and logic generation capabilities. I/O cells Product-term array and Logic Allocator Macrocells Register control generator Output enable generator I/O Cells The I/Os associated with each PAL block have a path directly back to that PAL block called local feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block interconnect line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide connections between any two signals in a device. The block feeder assigns block interconnect lines and local feedback lines to the PAL block inputs. MACH 5 Family 2 OE Generator Control Generator Block Feeder Product-term Array Block Interconnect Local Feedback Logic Alocator Macrocells I/Os Select devices have been discontinued. See Ordering Information section for product status. Input Register Path Interconnect Feeder Figure PAL Block Structure 20446G-002 Product-Term Array and Logic Allocator The product-term array uses the same sum-of-products architecture as PAL devices and consists of 32 inputs plus their complements and 64 product terms arranged in 16 clusters. A cluster is a sum-of-products function with either 3 of 4 product terms. Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of three or four product terms, but a given cluster can only be steered to one macrocell Table If only three product terms in a cluster are steered, the fourth can be used as an input to an XOR gate for separate logic generation and/or polarity control. The wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic allocation scheme in the MACH 5 device allows for the implementation of large equations up to 32 product terms with only one pass through the logic array. Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Table Product Term Steering Options for PT Clusters and Macrocells Available Clusters Macrocell Available Clusters C0, C1, C2, C3, C4 C0, C1, C2, C3, C4, C5 C0, C1, C2, C3, C4, C5, C6 C0, C1, C2, C3, C4, C5, C6, C7 C0, C1, C2, C3, C4, C5, C6, C7 C1, C2, C3, C4, C5, C6, C7, C8 C2, C3, C4, C5, C6, C7, C8, C9 C3, C4, C5, C6, C7, C8, C9, C10 C5, C6, C7, C8, C9, C10, C11, C12 C6, C7, C8, C9, C10, C11, C12, C13 C7, C8, C9, C10, C11, C12, C13, C14 C8, C9, C10, C11, C12, C13, C14, C15 C8, C9, C10, C11, C12, C13, C14, C15 C9, C10, C11, C12, C13, C14, C15 C10, C11, C12, C13, C14, C15 C11, C12, C13, C14, C15 MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. Macrocells The macrocells for MACH 5 devices consist of a storage element which can be configured for combinatorial, registered or latched operation Figure The D-type flip-flops can be configured as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell. Each PAL block has the capability to provide two input registers by using macrocells 0 and In order to use this option, these macrocells must be accessed via the I/O pins associated with macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be used as “buried” macrocells to drive device logic via the matrix. Logic Allocator 5-8 Clusters/ Control Bus Macrocell Prog. Polarity Mode Selection Figure Macrocell Diagram 20446G-003 Control Generator The control generator provides four configurable clock lines and three configurable set/reset lines to each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can be independently selected by any flip-flop within a block. The clock lines can be configured to provide synchronous global pin clocks and asynchronous product term clocks, sum term clocks, and latch enables Figure Three of the four global clocks, as well as two product-term clocks and one sum-term clock, are available per PAL block. Positive or negative edge clocking is available as well as advanced clocking features such as complementary and biphase clocking. Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful in applications such as fast data paths. A biphase clock line clocks flip-flops on both the positive and negative edges of the clock. The configuration options for the four clock lines per PAL block are as follows: Clock Line 0 Options Global clock 0, 1, 2, or 3 with positive or negative edge clock enable Product-term clock A*B*C Sum-term clock A+B+C Clock Line 1 Options Global clock 0, 1, 2, or 3 with positive edge clock enable Global clock 0, 1, 2, or 3 with negative edge clock enable MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. Global clock 0, 1, 2, or 3 with positive and negative edge clock enable biphase Clock Line 2 Options Global clock 0, 1, 2, or 3 with clock enable Clock Line 3 Options Complement of clock line 2 same clock enable Product-term clock if clock line 2 does not use clock enable PT 0:3 PINCLK 0:3 MUX 4TO1 0 IN 0 1 IN 1 2 IN 2 OUT 3 IN 3 F0 F1 MUX 4TO1 0 1 2 3 IN 0 IN 1 IN 2 OUT IN 3 F0 F1 CLKIN Clock Enable MUX 2TO1 N 0 OUT N 1 MUX 2TO1 /CLK CLK0 /CLK CLKEN1 BIPHASE CLKEN2 CLK1 PT 0:2 PT0 SET0/RST0 MUX 2TO1 PT1 OUT /PT1 ST SET1/RST1 MUX 4TO1 0 1 2 3 IN 0 IN 1 IN 2 OUT IN 3 F0 F1 MUX 2TO1 CLKIN Clock Enable CLK2 MUX 2TO1 /CLK2 PTCLK CLK3 Select devices have been discontinued. See Ordering Information section for product status. OE Generator There is one output enable OE generator per PAL block that generates two product-term driven output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL block can choose to be permanently enabled, permanently disabled, or choose one of the two product term output enables per PAL block Figure Output Enable Generator Internal Feedback External Feedback Figure Output Enable Generator and I/O Cell 20446G-006 MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. MACH 5 TIMING MODEL The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. The parameter, tBUF, is defined as the time it takes to go through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 5 timing model is shown in Figure Refer to the Technical Note entitled MACH 5 Timing and High Speed Design for a more detailed discussion about the timing parameters. External Feedback Internal Feedback COMB/DFF/ LATCH tS S/A tPDi tSLW tH S/A tCO S/A i Q tBUF tSAL tPDLi tHAL tGOAi INPUT REG/ INPUT LATCH tSIR S/A tCO S/A i Q tBLK tSEG tPL1 tPL2 tPL3 tSRR tSRi tCES tCEH tHIR S/A tSIL tPDILi tGOAi tHIL tSRi tSRR tCES tCEH PIN CLK Figure MACH 5 Timing Model 20446G-014 MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. MULTIPLE I/O AND DENSITY OPTIONS The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers to choose a device close to their logic density and I/O requirements, thus minimizing costs. For the same package type, every density has the same pin-out. With proper design considerations, a design can be moved to a higher or lower density part as required. IEEE - COMPLIANT BOUNDARY SCAN TESTABILITY Most MACH 5 devices have boundary scan registers and are compliant to the IEEE standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. IEEE - COMPLIANT IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All MACH 5 devices provide insystem programming ISP capability through their IEEE 1149.1-compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Boundary Scan Test Access Port as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. MACH 5 devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO software takes the JEDEC file output produced by design implementation software, along with information about the Boundary Scan chain, and creates a set of vectors that are used to drive the Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equipment can then be used to program MACH 5 devices during the testing of a circuit board. PCI COMPLIANT MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version published by the PCI Special Interest Group SIG . The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. MACH 5 devices provide the speed, drive, density, output enables and I/Os for the most complex PCI designs. MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS 1 Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of V, while they accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to V. Both the 3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use mixed-voltage design capability. Note Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to Application Note titled “Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices”. BUS-FRIENDLY INPUTS AND I/OS All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is a good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. POWER MANAGEMENT There are 4 power/speed options in each MACH 5 PAL block Table The speed and power tradeoff can be tailored for each design. The signal speed paths in the lower-power PAL blocks will be slower than those in the higher-power PAL blocks. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in a lower-power mode. In large designs, there may be several different speed requirements for different portions of the design. Table Power Levels High Speed/High Power 100% Power Medium High Speed/Medium High Power 67% Power Medium Low Speed/Medium Low Power 40% Power Low Speed/Low Power 20% Power PROGRAMMABLE SLEW RATE Each MACH 5 device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition 3 V/ns or for the lower noise transition 1 V/ns . For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. POWER-UP RESET/SET All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset delay time has elapsed. MACH 5 Family SECURITY BIT A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. Select devices have been discontinued. See Ordering Information section for product status. MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. MACH 5 PAL BLOCK 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63 Switch Matrix Output Enable Output Enable M1 M2 Logic Allocator C6 C7 C10 C11 M9 C12 C13 M10 C14 C15 M11 M13 M14 Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell Macro cell I/O Cell I/O Cell Cell Cell Cell Cell Cell I/O Cell I/O Cell Cell Cell Cell Cell Select devices have been discontinued. See Ordering Information section for product status. 20446G-008 MACH 5 Family CLK0 CLK1 CLK2 CLK3 Select devices have been discontinued. See Ordering Information section for product status. Block A/Macrocells 0-15 SEGMENT 0 Block D/Macrocells 0-15 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator Block Interconnect 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 Control 7 Generator 2 PT OE I/O Cells 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells Control 7 Generator 2 PT OE Block B/Macrocells 0-15 Block C/Macrocells 0-15 I2, I3 Block A/Macrocells 0-15 SEGMENT 2 Block D/Macrocells 0-15 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT Select devices have been discontinued. See Ordering Information section for product status. BLOCK DIAGRAM M5 LV -320/XXX Block A/Macrocells 0-15 SEGMENT 0 Block D/Macrocells 0-15 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator Block Interconnect 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 Control 7 Generator 2 PT OE I/O Cells 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells Control 7 Generator 2 PT OE Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block A/Macrocells 0-15 SEGMENT 4 Block D/Macrocells 0-15 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT Select devices have been discontinued. See Ordering Information section for product status. BLOCK DIAGRAM M5 LV -384/XXX Block A/Macrocells 0-15 SEGMENT 0 Block D/Macrocells 0-15 Block A/Macrocells 0-15 SEGMENT 5 Block D/Macrocells 0-15 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator Block Interconnect Block Interconnect 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells Control 7 Generator 2 PT OE Select devices have been discontinued. See Ordering Information section for product status. BLOCK DIAGRAM M5 LV -512/XXX Continued Block A/Macrocells 0-15 SEGMENT 0 Block D/Macrocells 0-15 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator Block Interconnect 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells Control 7 Generator 2 PT OE 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells Control 7 Generator 2 PT OE Block B/Macrocells 0-15 Block C/Macrocells 0-15 Block A/Macrocells 0-15 SEGMENT 7 Block D/Macrocells 0-15 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 Select devices have been discontinued. See Ordering Information section for product status. BLOCK DIAGRAM M5 LV -512/XXX Block A/Macrocells 0-15 SEGMENT 6 Block D/Macrocells 0-15 Block A/Macrocells 0-15 SEGMENT 5 Block D/Macrocells 0-15 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator Block Interconnect Block Interconnect 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells Control 7 Generator 2 PT OE Select devices have been discontinued. See Ordering Information section for product status. Select devices have been discontinued. See Ordering Information section for product status. ABSOLUTE MAXIMUM RATINGS Storage Temperature. -65°C to +150°C Device Junction Temperature Note 1 +130°C or +150°C Supply Voltage with Respect to Ground V to V DC Input Voltage V to V Static Discharge Voltage 2000 V Latchup Current -40°C to +85°C 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial C Devices Ambient Temperature TA Operating in Free Air 0°C to +70°C Supply Voltage VCC with Respect to Ground. V to V Industrial I Devices Ambient Temperature TA Operating in Free Air .-40°C to +85°C Supply Voltage VCC with Respect to Ground. V to V Operating ranges define those limits between which the functionality of the device is guaranteed. 5-V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Min Typ Max Unit Output HIGH Voltage IOH = mA, VCC = Min, VIN = VIH or VIL For M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384, M5-512 Devices IOH = -100 µA, VCC = Max, VIN = VIH or VIL Output HIGH Voltage IOH = mA, VCC = Min, VIN = VIH or VIL For M5-128, M5-192, M5-256 Devices IOH = mA, VCC = V, VIN = VIH or VIL Output LOW Voltage Note 2 IOL = +16 mA, VCC = Min, VIN = VIH or VIL Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs Note 3 Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs Note 3 Input HIGH Leakage Current Input LOW Leakage Current IOZH Off-State Output Leakage Current HIGH IOZL Off-State Output Leakage Current LOW Output Short-Circuit Current VIN = VCC = Max Note 4 VIN = 0, VCC = Max Note 4 Select devices have been discontinued. See Ordering Information section for product status. ABSOLUTE MAXIMUM RATINGS M5LV Storage Temperature. -65°C to +150°C Device Junction Temperature. +130°C Supply Voltage with Respect to Ground V to V DC Input Voltage V to V Static Discharge Voltage 2000 V Latchup Current -40°C to +85°C 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial C Devices Ambient Temperature TA Operating in Free Air 0°C to +70°C Supply Voltage VCC with Respect to Ground. V to V Industrial I Devices Ambient Temperature TA Operating in Free Air .-40°C to +85°C Supply Voltage VCC with Respect to Ground. V to V Operating ranges define those limits between which the functionality of the device is guaranteed. 3.3-V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Max Unit Output HIGH Voltage VCC = Min VIN = VIH or VIL IOH = -100 uA IOH = mA Output LOW Voltage VCC = Min VIN = VIH or VIL IOL = 100 uA IOL = 16 mA Note 1 Input HIGH Voltage VOUT VOH Min or VOUT VOL Max Note 2 Input LOW Voltage VOUT VOH Min or VOUT VOL Max Note 2 Input HIGH Leakage Current VIN = VCC = Max Note 3 Input LOW Leakage Current VIN = 0, VCC = Max Note 3 IOZH Off-State Output Leakage Current HIGH VOUT = VCC = Max, VIN = VIH or VIL Note 3 IOZL Off-State Output Leakage Current LOW VOUT = 0, VCC = Max, VIN = VIH or VIL Note 3 Output Short-Circuit Current VOUT = VCC = Max, VIN = VIH or VIL Note 4 -160 Notes Total IOL between ground pins should not exceed 64 mA. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH. Not more than one output should be shorted at one time. Duration of the short-circuit should not exceed one second. MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. M5 LV TIMING PARAMETERS OVER OPERATING RANGES1 Combinatorial Delay: Internal combinatorial propagation tPDi delay tPD Combinatorial propagation delay Registered Delays: tSS Synchronous clock setup time tSA Asynchronous clock setup time tHS Synchronous clock hold time tHA Asynchronous clock hold time tCOSi Synchronous clock to internal output tCOS Synchronous clock to output tCOAi Asynchronous clock to internal output tCOA Asynchronous clock to output Latched Delays: tSAL Latch setup time tHAL Latch hold time tPDLi Transparent latch internal tPDL Propagation delay through transparent latch tGOAi Gate to internal output tGOA Gate to output Input Register Delays: tSIRS Input register setup time using a synchronous clock tSIRA Input register setup time using an asynchronous clock tHIRS Input register hold time using a synchronous clock Input register hold time using an tHIRA asynchronous clock Input Latch Delays: tSIL Input latch setup time tHIL Input latch hold time tPDILi Transparent input latch Output Delays: tBUF Output buffer delay tSLW Slow slew rate delay tEA Output enable time tER Output disable time Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. M5 LV TIMING PARAMETERS OVER OPERATING RANGES1 CONTINUED Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Power Delays: tPL1 Power level 1 delay Note 2 tPL2 Power level 2 delay Note 2 tPL3 Power level 3 delay Note 2 Additional Cluster Delay: tPT Product term cluster delay Interconnect Delays: tBLK Block interconnect delay tSEG Segment interconnect delay Reset and Preset Delays: tSRi Asynchronous reset or preset to internal register output Asynchronous reset or preset to register output tSRR Reset and set register recovery time tSRW Asynchronous reset or preset width Clock Enable Delays: tCES Clock enable setup time tCEH Clock enable hold time Width: tWLS Global clock width low Note 3 tWHS Global clock width high Note 3 tWLA Product term clock width low tWHA Product term clock width high tGWA Gate width low for low transparent or high for high transparent tWIR Input register clock width low or high MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. M5 LV TIMING PARAMETERS OVER OPERATING RANGES1 CONTINUED Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Frequency: External feedback, PAL block level. Min of 1/ tWLS + tWHS or 1/ tSS + tCOS fMAX Internal feedback, PAL block level. Min of 1/ tWLS + tWHS or 1/ tSS +tCOSi No feedback PAL block level. Min of 1/ tWLS + tWHS or 1/ tSS + tHS External feedback, PAL block level. Min of 1/ tWLA + tWHA or 1/ tSA + tCOA fMAXA Internal feedback, PAL block level. Min of 1/ tWLA + tWHA or 1/ tSA +tCOAi No feedback, PAL block level. Min of 1/ tWLA + tWHA or 1/ tSA + tHA Maximum input register frequency fMAXI 1/ tSIRS+tHIRS or 1/ 2 x tWICW Notes See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site. Numbers in parentheses are for M5-128, M5-192, M5-256. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies fMAX/2 . MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. CAPACITANCE1 Parameter Symbol Parameter Description Test conditions Unit I/CLK pin VIN V V or 5 V, 25º C, 1 MHz CI/O I/O pin VOUT V V or 5 V, 25º C, 1 MHz These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where these parameters may be affected. ICC vs. FREQUENCY These curves represent the typical power consumption for a particular device at system frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency LSBs is placed in common PAL blocks, which are set to high power. The lowest frequency signals MSBs are placed in a common PAL block and set to lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book CD-ROM or Lattice web site. ICC CURVES AT HIGH /LOW POWER MODES VCC = 5 V or V, TA = 25º C M5 LV -512 high power M5 LV -384 high power 500 M5 LV -320 high power M5-256/1 and M5LV-25 high power 300 M5-192/1 high power M5 LV -512 low power M5-128/1 and M5LV-128 high power M5 LV -384 low power M5 LV -320 low power M5-256/1 and M5LV-256 low power M5-192/1 low power M5-128/1 and M5LV-128 low power ICC mA 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Frequency MHz Figure ICC Curves at High/Low Power Modes 20446G-048 MACH 5 Family ICC mA 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Select devices have been discontinued. See Ordering Information section for product status. VCC = 5 V, TA = 25º C 700 M5-256 high power 600 M5-192 high power 400 M5-128 high power 200 M5-256 low power M5-192 low power M5-128 low power Frequency MHz Figure ICC Curves at High/Low Power Modes 20446G-049 MACH 5 Family 100-PIN PQFP CONNECTION DIAGRAM Top View 100-Pin PQFP 68 I/O M5-128 M5LV-128* M5-192* M5-256* M5LV-256 M5-128 M5LV-128* M5-192* M5-256* M5LV-256 I/O52 3A7 2A7 0D13 I/O53 3A6 2A6 0D12 I/O54 3A5 2A5 0D11 I/O55 3A4 2A4 0D8 I/O56 3A3 2A3 0D7 I/O57 3A2 2A2 0D4 I/O58 3A1 2A1 0D3 I/O59 3A0 2A0 0D2 I/O60 0A0 0A2 I/O61 0A1 0A3 I/O62 0A2 0A4 I/O63 0A3 0A7 I/O64 0A4 0A8 I/O65 0A5 0A11 I/O66 0A6 0A12 I/O67 0A7 0A13 Select devices have been discontinued. See Ordering Information section for product status. 0A14 0A12 I/O0 0B13 I/O1 0B12 I/O2 0B11 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 I1/CLK1 I/O9 1B3 I/O10 1B4 I/O11 1B7 I/O12 1B8 I/O13 1B11 I/O14 1B12 I/O15 1B13 I/O16 1A14 1A12 I/O17 I/O51 3A12 2A12 0D14 I/O50 3B13 2B13 0C13 I/O49 3B12 2B12 0C12 I/O48 3B11 2B11 0C11 I/O47 3B8 2B8 0C8 I/O46 3B7 2B7 0C7 I/O45 3B4 2B4 0C4 I/O44 3B3 2B3 0C3 I/O43 3B2 2B2 0C2 I3/CLK3 I2/CLK2 I/O42 2B2 2C2 1C2 I/O41 2B3 2C3 1C3 I/O40 2B4 2C4 1C4 I/O39 2B7 2C7 1C7 I/O38 2B8 2C8 1C8 Select devices have been discontinued. See Ordering Information section for product status. 0A14 0A12 I/O0 0B13 I/O1 0B12 I/O2 0B11 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 I1/CLK1 I/O9 1B3 I/O10 1B4 I/O11 1B7 I/O12 1B8 I/O13 1B11 I/O14 1B12 I/O15 1B13 I/O16 1A14 1A12 I/O17 I/O51 3A12 2A12 0D14 I/O50 3B13 2B13 0C13 I/O49 3B12 2B12 0C12 I/O48 3B11 2B11 0C11 I/O47 3B8 2B8 0C8 I/O46 3B7 2B7 0C7 I/O45 3B4 2B4 0C4 I/O44 3B3 2B3 0C3 I/O43 3B2 2B2 0C2 I3/CLK3 I2/CLK2 I/O42 2B2 2C2 1C2 I/O41 2B3 2C3 1C3 I/O40 2B4 2C4 1C4 I/O39 2B7 2C7 1C7 I/O38 2B8 2C8 1C8 Select devices have been discontinued. See Ordering Information section for product status. 0A14 0A12 I/O0 0B13 I/O1 0B12 I/O2 0B11 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 I1/CLK1 I/O9 1B3 I/O10 1B4 I/O11 1B7 I/O12 1B8 I/O13 1B11 I/O14 1B12 I/O15 1B13 I/O16 1A14 1A12 I/O17 I/O54 3A12 0D14 I/O53 3B13 0C13 I/O52 3B12 0C12 I/O51 3B11 0C11 I/O50 3B8 0C8 I/O49 3B7 0C7 I/O48 3B4 0C4 I/O47 3B3 0C3 I/O46 3B2 0C2 I3/CLK3 I2/CLK2 I/O45 2B2 1C2 I/O44 2B3 1C3 I/O43 2B4 1C4 I/O42 2B7 1C7 I/O41 2B8 1C8 Select devices have been discontinued. See Ordering Information section for product status. 144-PIN PQFP CONNECTION DIAGRAM Top View 144-Pin PQFP M5-128 M5LV-128* M5-192* M5-256* M5LV-256* I/O89 3D11 0D11 0D1 I/O90 3D12 0D8 0D0 I/O91 0D12 0D7 0A0 I/O92 0D11 0D4 0A1 I/O93 0D8 0D3 0A2 I/O94 0D7 0D2 0A3 I/O95 0D4 0A2 0A4 I/O96 0D3 0A3 0A5 I/O97 0A1 0A4 0A6 I/O98 0A2 0A5 0A7 I/O99 0A3 0A6 0A8 I/O100 0A4 0A7 A10 I/O101 0A5 0A8 0A11 I/O102 0A6 0A10 0A12 I/O103 0A7 0A11 0A13 0A14 0A12 0A8 I/O0 0B13 0A13 0A9 I/O1 0B12 0A14 0A10 I/O2 0B11 0B13 0A11 I/O3 0B10 0B12 0A12 I/O4 0B8 0B11 0B13 I/O5 0B7 0B8 0B12 I/O6 0B6 0B5 0B11 I/O7 0B5 0B4 0B8 I/O8 0B4 0B3 0B5 Select devices have been discontinued. See Ordering Information section for product status. 0A14 0A8 I/O0 0B13 0A9 I/O1 0B12 0A10 I/O2 0B11 0A11 I/O3 0B10 0A12 I/O4 0B8 0B13 I/O5 0B7 0B12 I/O6 0B6 0B11 I/O7 0B5 0B8 I/O8 0B4 0B5 I/O9 0B3 0B4 I/O10 0B2 0B3 I/O11 0B1 0B2 I/O12 I0/CLK0 I1/CLK1 1B1 1B2 I/O13 1B2 1B3 I/O14 1B3 1B4 I/O15 1B4 1B5 I/O16 1B5 1B8 I/O17 1B6 1B11 I/O18 1B7 1B12 I/O19 1B8 1B13 I/O20 1B10 1A12 I/O21 1B11 1A11 I/O22 1B12 1A10 I/O23 1B13 1A9 I/O24 1A14 1A8 I/O25 I/O77 3A8 0D14 I/O76 3A9 0C13 Select devices have been discontinued. See Ordering Information section for product status. 160-PIN PQFP CONNECTION DIAGRAM Top View 160-Pin PQFP 128, 192, 256 Macrocells M5-128 M5LV-128 M5-192 M5-256 M5LV-256 M5-128 M5LV-128 M5-192 M5-256 M5LV-256 I/O92 3A7 2A11 0D13 I/O93 3A6 2A10 0D12 I/O94 3A5 2A9 0D11 I/O95 3A4 2A8 0D10 I/O96 3A3 2A7 0D9 I/O97 3A2 2A6 0D8 I/O98 3A1 2A5 0D7 I/O99 3A0 2A4 0D6 I/O100 3D3 2A3 0D5 I/O101 3D4 2A2 0D4 I/O102 3D7 0D13 0D3 I/O103 3D8 0D12 0D2 I/O104 3D11 0D11 0D1 I/O105 3D12 0D8 0D0 I/O106 0D12 0D7 0A0 I/O107 0D11 0D4 0A1 I/O108 0D8 0D3 0A2 I/O109 0D7 0D2 0A3 I/O110 0D4 0A2 0A4 I/O111 0D3 0A3 0A5 I/O112 0A0 0A4 0A6 I/O113 0A1 0A5 0A7 I/O114 0A2 0A6 0A8 I/O115 0A3 0A7 0A9 I/O116 0A4 0A8 0A10 I/O117 0A5 0A9 0A11 I/O118 0A6 0A10 0A12 I/O119 0A7 0A11 0A13 0A14 0A12 0A8 I/O0 0A15 0A13 0A9 Select devices have been discontinued. See Ordering Information section for product status. 160-PIN PQFP WITH INTERNAL HEAT SPREADER CONNECTION DIAGRAM Top View 160-Pin PQFP 320, 384, 512 Macrocells M5-320* M5LV-320 M5-384* M5LV-384 M5-512* M5LV-512 M5-320* M5LV-320 M5-384* M5LV-384 M5-512* M5LV-512 I/O92 6A13 4B2 3B2 I/O93 6A12 4B3 3B3 I/O94 6A11 4B4 3B4 I/O95 6A8 4B7 3B7 I/O96 6A7 4B8 3B8 I/O97 6A4 4B11 3B11 I/O98 6A3 4B12 3B12 I/O99 6A2 4B13 3B13 I/O100 6B3 5B12 4B12 I/O101 6B4 5B11 4B11 I/O102 6B7 5B8 4B8 I/O103 6B8 5B7 4B7 I/O104 6B11 5B4 4B4 I/O105 6B12 5B3 4B3 I/O106 7B12 5A3 4A3 I/O107 7B11 5A4 4A4 I/O108 7B8 5A7 4A7 I/O109 7B7 5A8 4A8 I/O110 7B4 5A11 4A11 I/O111 7B3 5A12 4A12 I/O112 7A2 0B13 I/O113 7A3 0B12 I/O114 7A4 0B11 I/O115 7A7 0B8 I/O116 7A8 0B7 I/O117 7A11 0B4 I/O118 7A12 0B3 I/O119 7A13 0B2 I/O0 I/O1 I/O2 Select devices have been discontinued. See Ordering Information section for product status. 208-PIN PQFP CONNECTION DIAGRAM Top View 208-Pin PQFP 256 Macrocells M5-256 M5LV-256 I/O133 3D7 I/O134 3D8 I/O135 3D9 I/O136 3D10 I/O137 3D11 I/O138 3D12 I/O139 3D13 I/O140 0D13 I/O141 0D12 I/O142 0D11 I/O143 0D10 I/O144 0D9 I/O145 0D8 I/O146 0D7 I/O147 0D6 I/O148 0D5 I/O149 0D4 I/O150 0D3 I/O151 0D2 I/O152 0A0 I/O153 0A1 I/O154 0A2 I/O155 0A3 I/O156 0A4 I/O157 0A5 I/O158 0A6 I/O159 0A7 I/O0 I/O1 0A10 I/O2 0A11 I/O3 0A12 I/O4 0A13 Select devices have been discontinued. See Ordering Information section for product status. 208-PIN PQFP WITH INTERNAL HEAT SPREADER CONNECTION DIAGRAM Top View 208-Pin PQFP 320, 384, 512 Macrocells M5-320 M5LV-320 M5-384 M5LV-384 M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 M5-512 M5LV-512 I/O120 6A13 4B2 I/O121 6A12 4B3 I/O122 6A11 4B4 I/O123 6A8 4B7 I/O124 6A7 4B8 I/O125 6A4 4B11 3B11 I/O126 6A3 4B12 3B12 I/O127 6A2 4B13 3B13 I/O128 6B0 5B15 4B15 I/O129 6B1 5B14 4B14 I/O130 6B2 5B13 4B13 I/O131 6B3 5B12 4B12 I/O132 6B4 5B11 4B11 I/O133 6B5 5B10 4B10 I/O134 6B6 5B9 I/O135 6B7 5B8 I/O136 6B8 5B7 I/O137 6B11 5B4 I/O138 6B12 5B3 I/O139 6B13 5B2 I/O140 7B13 5A2 I/O141 7B12 5A3 I/O142 7B11 5A4 I/O143 7B8 5A7 I/O144 7B7 5A8 I/O145 7B6 5A9 I/O146 7B5 5A10 4A10 I/O147 7B4 5A11 4A11 I/O148 7B3 5A12 4A12 I/O149 7B2 5A13 4A13 I/O150 7B1 5A14 4A14 Select devices have been discontinued. See Ordering Information section for product status. 256-BALL BGA CONNECTION DIAGRAM M5-320 Bottom View Macrocell Association 256-Ball BGA 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A GND 0B2 GND 0B13 4A14 GND 4A8 4A4 GND 4B4 4B8 GND 4B14 3B13 GND A B GND 0A3 0B8 0B11 4A15 4A11 4A10 4A6 4A3 4A0 4B0 4B3 4B6 4B10 4B11 4B15 3B11 3B8 3B2 GND B C 0D15 0A8 VCC 0B3 0B4 0B12 4A13 4A9 4A5 4A1 4B1 4B5 4B9 4B13 3B12 3B4 3B3 VCC 3A3 3A11 C D 0D13 0A11 0A2 VCC 0B7 VCC 4A12 4A7 4A2 4B2 4B7 4B12 VCC 3B7 VCC 3A2 3A8 3D15 D E 0D10 0A13 0A4 TDI TDO 3A4 3A13 3D12 E Pin Designations CLK = Clock GND = Ground = Input I/O = Input/Output NC = No Connect VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 4 D 15 F GND 0D12 0A12 0A7 3A7 3A12 3D13 GND F G 0D7 0D8 0D14 VCC VCC 3D14 3D9 3D7 G MACH 5 Family H GND 0D4 0D9 0D11 3D11 3D10 3D8 GND H J 0D2 0D3 0D5 0D6 3D6 3D5 3D4 3D3 J K GND IO/CLK0 0D0 0D1 3D1 3D0 I3/CLK3 3D2 K Macrocell 0-15 PAL Block A-D Segment 0-4 L 1D2 I1/CLK1 1D0 1D1 2D1 2D0 I2/CLK2 GND L M 1D3 1D4 1D5 1D6 2D6 2D5 2D3 2D2 M N GND 1D8 1D10 1D11 2D11 2D9 2D4 GND N P 1D7 1D9 1D14 VCC Select devices have been discontinued. See Ordering Information section for product status. 352-BALL BGA CONNECTION DIAGRAM M5-512, M5LV-512 Bottom View I/O Pin-outs 352-Ball BGA 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A NC GND NC I/O51 GND I/O73 I/O80 I/O87 GND I/O101 NC I/O114 GND I/O128 I/O134 I/O142 GND I/O156 I/O162 GND NC GND NC GND NC A B NC GND NC I/O52 I/O68 I/O74 I/O81 I/O88 I/O95 I/O102 I/O107 I/O115 I/O122 I/O129 I/O135 I/O143 I/O150 I/O157 I/O163 I/O169 I/O176 I/O183 I/O188 GND NC B C GND I/O11 TDI I/O53 I/O69 I/O75 I/O82 I/O89 I/O96 I/O103 I/O108 I/O116 I/O123 I/O130 I/O136 I/O144 I/O151 I/O158 I/O164 I/O170 I/O177 I/O184 NC C D I/O0 I/O12 I/O32 VCC I/O70 I/O76 I/O83 I/O90 VCC I/O104 I/O109 I/O117 VCC I/O131 I/O137 I/O145 VCC I/O159 I/O165 I/O171 I/O178 VCC TDO I/O205 I/O224 GND D E NC I/O13 I/O33 I/O54 I/O189 I/O206 I/O225 NC E F GND I/O14 I/O34 I/O55 I/O190 I/O207 I/O226 I/O245 F G I/O1 I/O15 I/O35 VCC I/O191 I/O208 I/O227 GND G H I/O2 I/O16 I/O36 I/O56 VCC I/O209 I/O228 I/O246 H J GND I/O17 I/O37 VCC I/O192 I/O210 I/O229 I/O247 J K I/O3 I/O18 I/O38 I/O57 VCC I/O211 I/O230 GND K Pin Designations CLK = Clock GND = Ground = Input I/O = Input/Output NC = No Connect VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out L I/O4 I/O19 I/O39 I/O58 I/O193 I/O212 I/O231 I/O248 L MACH 5 Family M I/O5 I/O20 I/O40 I/O59 I/O194 I/O213 I/O232 I/O249 M N GND I/O21 I0/CLK0 VCC I/O195 I/O214 I/O233 I3/CLK3 N P I1/CLK1 I/O22 I/O41 I/O60 VCC I2CLK2 I/O234 GND P R I/O6 I/O23 I/O42 I/O61 Select devices have been discontinued. See Ordering Information section for product status. 352-BALL BGA CONNECTION DIAGRAM M5-512, M5LV-512 Bottom View Macrocell Association 352-Ball BGA 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A NC GND NC 7A10 GND 7A5 7A0 7B1 GND 7B7 NC 7B14 GND 6B14 6B10 6B6 GND 6B1 6A1 GND NC GND NC GND NC A B NC GND NC 7A13 7A9 7A6 7A2 7B0 7B3 7B6 7B10 7B13 7B15 6B13 6B9 6B5 6B2 6A0 6A4 6A6 6A9 6A12 6A14 GND NC B C GND 0A1 TDI 7A14 7A11 7A7 7A3 7A1 7B2 7B5 7B9 7B12 6B15 6B12 6B8 6B4 6B0 6A2 6A5 6A8 6A10 6A13 NC C D 0A6 0A3 0A2 VCC 7A15 7A12 7A8 7A4 VCC 7B4 7B8 7B11 VCC 6B11 6B7 6B3 VCC 6A3 6A7 6A11 6A15 VCC TDO 5A1 5A2 GND D E NC 0A8 0A5 0A0 5A0 5A4 5A5 NC E F GND 0A9 0A7 0A4 5A3 5A7 5A9 5A12 F G 0A13 0A12 0A10 VCC 5A6 5A8 5A14 GND G H 0D15 0A15 0A14 0A11 VCC 5A10 5A15 5D15 H Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output NC = No Connect VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out J GND 0D13 0D14 VCC 5A11 5A13 5D13 5D11 J 7 D 15 K 0D9 0D10 0D11 0D12 VCC 5D14 5D10 GND K L 0D5 0D6 0D7 0D8 5D12 5D9 5D8 5D6 L MACH 5 Family M 0D1 0D2 0D4 0D3 5D7 5D5 5D4 5D3 M N GND 0D0 I0/CLK0 VCC 5D2 5D1 5D0 I3/CLK3 N Macrocell 0-15 PAL Block A-D Segment 0-7 P I1/CLK1 1D0 1D1 1D2 VCC I2/CLK2 4D0 GND P R 1D3 1D4 1D5 1D7 4D3 4D4 4D2 4D1 R T 1D6 1D8 1D9 1D12 4D8 4D7 4D6 4D5 T U GND 1D10 1D14 VCC 4D12 4D11 4D10 4D9 U V 1D11 1D13 1A13 1A11 Select devices have been discontinued. See Ordering Information section for product status. Select devices have been discontinued. See Ordering Information section for product status. 5V M5 ORDERING INFORMATION1,2 Lattice standard products are available in several packages and operating ranges. The order number Valid Combination is formed by a combination of the elements below. M5- 512 /256 -7 SA C FAMILY TYPE M5- = MACH 5-V VCC MACROCELL DENSITY 128 = 128 Macrocells 192 = 192 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells I/Os /68 /104 /120 /160 /192 /256 = 68 I/Os in 100-pin PQFP or TQFP = 104 I/Os in 144-pin PQFP or TQFP = 120 I/Os in 160-pin PQFP = 160 I/Os in 208-pin PQFP = 192 I/Os in 256-ball BGA = 256 I/Os in 352-ball BGA Note See below for valid device/package combinations. M5-128/1, M5-192/1 and M5-256/1 recommended for new designs. M5-128/68 M5-128/104 M5-128/120 M5-192/68 M5-192/120 M5-256/68 M5-256/120 M5-256/160 Valid Combinations Commercial -5, -7, -10, -12, -15 Industrial -7, -10, -12, -15, -20 YC, VC, YI, VI YC1, YI1 YC, YI VC, VI YC, YI VC, VI YC, YI YC, YI Device Marking Actual device marking differs from the ordering part number OPN . All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e., M5-512/2567AC-10AI. M5-128/104-xxYC/1 and M5-128/104-xxYI/1 have been discontinued per PCN Contact Rochester Electronics for available inventory. OPERATING CONDITIONS C = Commercial 0°C to +70°C I = Industrial -40°C to +85°C PACKAGE TYPE Y = Plastic Quad Flat Pack PQFP V = Thin Quad Flat Pack TQFP SA = Ball Grid Array BGA SPEED -5 = ns tPD -6 = ns tPD -7 = ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD M5-320/160 M5-320/192 M5-384/160 M5-512/160 M5-512/256 Valid Combinations Commercial -6, -7, -10, -12, -15 Industrial -7, -10, -12, -15, -20 YC, YI SAC, SAI YC, YI YC, YI SAC, SAI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH 5 Family Select devices have been discontinued. See Ordering Information section for product status. 3.3V M5LV ORDERING INFORMATION1 Lattice standard products are available in several packages and operating ranges. The order number Valid Combination is formed by a combination of the elements below. M5LV- 512 /256 -7 SA C FAMILY TYPE M5LV- = MACH 5 Low Voltage 3.3-V VCC MACROCELL DENSITY 128 = 128 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells I/Os /68 = 68 I/Os in 100-pin PQFP or TQFP /74 = 74 I/Os in 100-pin TQFP /104 = 104 I/Os in 144-pin PQFP or TQFP /120 = 120 I/Os in 160-pin PQFP /160 = 160 I/Os in 208-pin PQFP /256 = 256 I/Os in 352-ball BGA Note See below for valid device/package combinations. OPERATING CONDITIONS C = Commercial 0°C to +70°C I = Industrial -40°C to +85°C PACKAGE TYPE Y = Plastic Quad Flat Pack PQFP V = Thin Quad Flat Pack TQFP SA = Ball Grid Array BGA SPEED -5 = ns tPD -6 = ns tPD -7 = ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD M5LV-128/68 M5LV-128/74 M5LV-128/104 M5LV-128/120 M5LV-256/68 M5LV-256/74 M5LV-256/104 M5LV-256/120 M5LV-256/160 Valid Combinations Commercial -5, -7, -10, -12 Industrial -7, -10, -12, -15 VC, VI VC, VI VC, VI YC, YI YC, YI VC, VI VC, VI YC, YI YC, YI Device Marking Actual device marking differs from the ordering part number OPN . All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e., M5LV-512/2567AC-10AI. M5LV-320/120 M5LV-320/160 M5LV-384/120 M5LV-384/160 M5LV-512/120 M5LV-512/160 M5LV-512/256 Valid Combinations Commercial -6, -7, -10, -12, -15 Industrial -10, -12, -15, -20 YC, YI YC, YI YC, YI YC, YI YC, YI YC, YI SAC, SAI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH 5 Family |
| More datasheets: M5LV-384/160-10YC | M5LV-384/120-7YI | M5LV-384/120-7YC | M5LV-384/120-6YC | M5LV-320/160-10YC | M5LV-384/120-15YI | M5LV-512/120-10YI | M5LV-384/120-12YI | M5LV-384/120-12YC | M5LV-384/120-10YI |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M5LV-384/120-10YC Datasheet file may be downloaded here without warranties.