LF500-PAC-EV

LF500-PAC-EV Datasheet

Part	Datasheet
LF500-PAC-EV	LF500-PAC-EV (pdf)

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ispXPGA Evaluation Board User’s Guide October 2004 ebug02_02 Lattice Semiconductor ispXPGA Evaluation Board User’s Guide Introduction The ispXPGA Evaluation Board is a versatile platform that enables the user to program, evaluate, and de-bug a design for the Lattice ispXPGA architecture. The board features a 900-ball fpBGA ispXPGA device with SMA connectors for access to the device’s High Speed Interface sysHSI and other I/Os. Connectors are also available to access general-purpose I/Os. Termination is provided for selected I/Os for LVDS operation. • Power management provided via Power Manager device • On-board 20MHz oscillator • Multiple integrated Low Drop-Out LDO regulators provide power from single 5V supply • programming support • Jumperless implementation • Cable pDS4102-DL2A included • 900-ball fpBGA ispXPGA device ispXPGA 1200 or ispXPGA 500 Figure ispXPGA Evaluation Board Electrical, Mechanical and Environmental The nominal board dimensions are inches by 5 inches. The environmental are as follows • Operating temperature 0°C to 55°C • Storage temperature -40°C to 75°C • Humidity < 95% without condensation Lattice Semiconductor ispXPGA Evaluation Board User’s Guide • 5VDC input, accessible via banana jacks or the included 5V, 4A AC adapter Holes are included at the corners of the PCB to provide attachment of vertical stand-offs. The pads at these holes are electrically Resources relating to the ispXPGA Evaluation Board, including a simple demonstration design, can be found on the Lattice web site at Table Embedded Functions Description 20MHz clock Reset Source On-board oscillator ispPAC device ispXPGA Pin GCLK0 R3 Global RST AK28 AND I/O pin AF21 Notes 3.3V TTL output Active low by default, programmable via ispPAC ispXPGA Device The board features an ispXPGA device in a 900-ball fpBGA package. from a compatible layout, it is also possible to use an ispXPGA device in the smaller 516-ball fpBGA package. This provides a future option to evaluate devices with a smaller density. ispPAC-POWR1208 Power Manager Device The Power Manager device controls the sequencing and monitoring of the various independent power supplies available on the ispXPLD board. Each supply can be activated in stages, with programmable delay increments. As the Power Manager device enables each LDO, a corresponding LED deactivates for visual The Power Manager design and JEDEC can be downloaded from the Lattice web site. The device is shipped preprogrammed with this default For a complete description of the operation of the ispPAC-POWR1208 device and the default design used on this board, refer to the ispPAC-POWR1208 data sheet and documentation PAC-Designer is the design software for the ispPAC-POWR1208 . These are available on the Lattice web site at VCCO The ispXPGA device supports multiple I/O standards and individual I/O bank supply pins for simultaneous support of different interfaces. The ispXPGA evaluation board is set by default to supply 2.5V to all I/O banks. This is adjustable via the addition of resistors. For alternate supply levels, resistor values can be installed as described in Figure Figure I/O Voltage Adjustments From LDO Output R Fixed TOP R User TOP To LDO FB R Fixed BOT R User BOT User-installable voltage set resistors Lattice Semiconductor

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ispXPGA Evaluation Board

User’s Guide

October 2004 ebug02_02

Lattice Semiconductor
ispXPGA Evaluation Board User’s Guide

Introduction

The ispXPGA Evaluation Board is a versatile platform that enables the user to program, evaluate, and de-bug a design for the Lattice ispXPGA architecture. The board features a 900-ball fpBGA ispXPGA device with SMA connectors for access to the device’s High Speed Interface sysHSI and other I/Os. Connectors are also available to access general-purpose I/Os. Termination is provided for selected I/Os for LVDS operation.
• Power management provided via Power Manager device
• On-board 20MHz oscillator
• Multiple integrated Low Drop-Out LDO regulators provide power from single 5V supply
• programming support
• Jumperless implementation
• Cable pDS4102-DL2A included
• 900-ball fpBGA ispXPGA device ispXPGA 1200 or ispXPGA 500

Figure ispXPGA Evaluation Board

Electrical, Mechanical and Environmental

The nominal board dimensions are inches by 5 inches. The environmental are as follows
• Operating temperature 0°C to 55°C
• Storage temperature -40°C to 75°C
• Humidity < 95% without condensation

Lattice Semiconductor
ispXPGA Evaluation Board User’s Guide
• 5VDC input, accessible via banana jacks or the included 5V, 4A AC adapter

Holes are included at the corners of the PCB to provide attachment of vertical stand-offs. The pads at these holes are electrically

Resources relating to the ispXPGA Evaluation Board, including a simple demonstration design, can be found on the Lattice web site at

Table Embedded Functions

Description 20MHz clock

Reset

Source On-board oscillator
ispPAC device
ispXPGA Pin GCLK0 R3 Global RST AK28 AND I/O pin AF21

Notes 3.3V TTL output Active low by default, programmable via ispPAC
ispXPGA Device

The board features an ispXPGA device in a 900-ball fpBGA package. from a compatible layout, it is also possible to use an ispXPGA device in the smaller 516-ball fpBGA package. This provides a future option to evaluate devices with a smaller density.
ispPAC-POWR1208 Power Manager Device

The Power Manager device controls the sequencing and monitoring of the various independent power supplies available on the ispXPLD board. Each supply can be activated in stages, with programmable delay increments. As the Power Manager device enables each LDO, a corresponding LED deactivates for visual

The Power Manager design and JEDEC can be downloaded from the Lattice web site. The device is shipped preprogrammed with this default

For a complete description of the operation of the ispPAC-POWR1208 device and the default design used on this board, refer to the ispPAC-POWR1208 data sheet and documentation PAC-Designer is the design software for the ispPAC-POWR1208 . These are available on the Lattice web site at

VCCO

The ispXPGA device supports multiple I/O standards and individual I/O bank supply pins for simultaneous support of different interfaces. The ispXPGA evaluation board is set by default to supply 2.5V to all I/O banks. This is adjustable via the addition of resistors. For alternate supply levels, resistor values can be installed as described in Figure

Figure I/O Voltage Adjustments

From LDO Output

R Fixed TOP

R User TOP

To LDO FB

R Fixed BOT

R User BOT

User-installable voltage set resistors

Lattice Semiconductor

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Datasheet ID: LF500-PAC-EV 645483