LC51024VG-5F484C
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LC5768VG-5F484C (pdf) |
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PDF Datasheet Preview |
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ispMACHTM 5000VG Family December 2001 3.3V In-System Programmable SuperBIGT,M SuperWIDETM High Density PLDs Data Sheet • High Density • 768 to 1,024 macrocells • 196 to 384 I/Os • sysCLOCK PLL Timing Control • Multiply and divide factors between 1 and 32 • Clock shifting capability ± 3.5ns in 500ps steps • Multiple output frequencies • External feedback capability for board-level clock deskew • LVDS/LVPECL clock input capability • High Speed Logic Implementation • SuperWIDE 68-input logic block • Up to 160 product terms per output • Hierarchical routing structure provides fast interconnect • sysIO Capability • LVCMOS and • LVTTL • SSTL 2 I & II • SSTL 3 I & II • CTT • HSTL I & III • PCI-X, PCI • GTL+ • AGP-1X • 5V tolerance • Programmable drive strength • Ease of Design • Product term sharing • Extensive clocking and OE capability • Easy System Integration • 3.3V power supply • Hot socketing • Input pull-up, pull-down or bus-keeper • Open drain capability • Slew rate control • Macrocell-based power management • IEEE boundary scan testable • In-system programmable via IEEE 1532 ISC compliant interface ispMACH 5000VG Introduction The ispMACH 5000VG represents the third generation of Lattice’s SuperWIDE CPLD architecture. Through their wide 68-input blocks, these devices give improved speed performance for typical designs over architectures with fewer inputs. The ispMACH 5000VG takes the unique of the SuperWIDE architecture and extends it to higher densities referred to as SuperBIG, by using the combination of an innovative product term architecture and a twotiered hierarchical routing architecture. Additionally, sysCLOCK and sysIO capabilities have been added to maximize system-level performance and integration. Table ispMACH 5000VG Family Selection Guide Macrocells User I/O Options tPD ns tS Set-up with 0 Hold ns tCO ns fMAX MHz Supply Voltage V Package ispMACH 5768VG 768 196/304 178 3.3V 256-ball fpBGA 484-ball fpBGA ispMACH 51024VG 1,024 304/384 178 3.3V 484-ball fpBGA 676-ball fpBGA 5kvg_09 Lattice Semiconductor Figure Functional Block Diagram ispMACH 5000VG Family Data Sheet RESETB GOE1 GOE2 TOE VCCO0 VREF0 GCLK0 VCCP0 GNDP0 GCLK1 VREF1 VCCO1 I/O Bank 0 I/O Bank 3 PLL0 Global Routing Pool PLL1 I/O Bank 1 I/O Bank 2 VCCO3 VREF3 GCLK3 VCCP1 GNDP1 GCLK2 VREF2 VCCO2 TDI TDO TMS TCK VCCJ Overview Ordering Information Commercial Package Pin Count Macrocells Voltage LC51024VG-5F484C fpBGA 1024 LC51024VG-75F484C fpBGA 1024 LC51024VG-10F484C fpBGA 1024 LC51024VG-5F676C fpBGA 1024 LC51024VG-75F676C fpBGA 1024 LC51024VG-10F676C fpBGA 1024 LC5768VG-5F256C fpBGA LC5768VG-75F256C fpBGA LC5768VG-10F256C fpBGA LC5768VG-5F484C fpBGA LC5768VG-75F484C fpBGA LC5768VG-10F484C fpBGA Note the ispMACH 5000VG family is dual-marked with both Commercial and Industrial grades. The Commercial speed grade is one speed grade faster i.e. LC51024VG-75F484C than the Industrial speed grade i.e. LC51024VG-10F484I . Lattice Semiconductor ispMACH 5000VG Family Data Sheet Industrial Package Pin Count Macrocells Voltage LC51024VG-75F484I |
More datasheets: LC5768VG-10F484C | LC5768VG-10F256C | LC5768VG-10F256I | LC51024VG-10F676C | LC51024VG-10F676I | LC5768VG-75F484I | LC5768VG-10F484I | LC5768VG-12F256I | LC5768VG-12F484I | LC5768VG-5F256C |
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