GAL16LV8D-3LJN

GAL16LV8D-3LJN Datasheet

Product Line GAL16LV8C GAL16LV8D

Part	Datasheet
GAL16LV8D-3LJN	GAL16LV8D-3LJN (pdf)

Related Parts	Information
GAL16LV8C-10LJN	GAL16LV8C-10LJN
GAL16LV8C-15LJN	GAL16LV8C-15LJN
GAL16LV8D-5LJN	GAL16LV8D-5LJN

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Device Datasheet June 2010 All Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line GAL16LV8C GAL16LV8D Ordering Part Number GAL16LV8C-7LJ GAL16LV8C-7LJN GAL16LV8C-10LJ GAL16LV8C-10LJN GAL16LV8C-15LJ GAL16LV8C-15LJN GAL16LV8D-3LJ GAL16LV8D-3LJN GAL16LV8D-5LJ GAL16LV8D-5LJN Product Status Reference PCN#06-07 Discontinued PCN#09-10 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone 503 268-8000 z FAX 503 268-8347 Internet: LePAOaavpdact-kiliFaaorgbneelsee! GAL16LV8 Low Voltage E2CMOS PLD Generic Array Logic Functional Block Diagram • HIGH PERFORMANCE TECHNOLOGY I/CLK ns Maximum Propagation Delay Fmax = 250 MHz ns Maximum from Clock Input to Data Output Advanced CMOS Technology 8 OLMC I/O/Q • 3.3V LOW VOLTAGE 16V8 ARCHITECTURE JEDEC-Compatible 3.3V Interface Standard 5V Compatible Inputs I/O Interfaces with Standard 5V TTL Devices S GAL16LV8C • ACTIVE PULL-UPS ON ALL PINS GAL16LV8D Only • E2 CELL TECHNOLOGY E D Reconfigurable Logic Reprogrammable Cells 100% Tested/100% Yields IC E High Speed Electrical Erasure <100ms 20 Year Data Retention • EIGHT OUTPUT LOGIC MACROCELLS Maximum Flexibility for Complex Logic Designs V U Programmable Output Polarity • PRELOAD AND POWER-ON RESET OF ALL REGISTERS 100% Functional Testability E IN • APPLICATIONS INCLUDE Glue Logic for 3.3V Systems DMA Control State Machine Control D T High Speed Graphics Processing Standard Logic Speed Upgrade • ELECTRONIC SIGNATURE FOR IDENTIFICATION L N • LEAD-FREE PACKAGE OPTIONS Pin Configuration PROGRAMMABLE AND-ARRAY 64 X 32 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/OE L O The GAL16LV8D, at ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V A C signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable E2 floating gate technology. High speed erase times <100ms allow the devices to be repro- IS grammed quickly and efficiently. The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features GAL16LV8 Ordering Information Conventional Packaging Commercial Grade Specifications Tpd ns Tsu ns Tco ns Icc mA Ordering # Package 70 GAL16LV8D-3LJ 20-Lead PLCC 70 GAL16LV8D-5LJ 20-Lead PLCC 65 GAL16LV8C-7LJ1 20-Lead PLCC 65 GAL16LV8C-10LJ 65 GAL16LV8C-15LJ 20-Lead PLCC 20-Lead PLCC Lead-Free Packaging S Commercial Grade Specifications Tpd ns Tsu ns Tco ns Icc mA Ordering # Package 70 GAL16LV8D-3LJN 70 GAL16LV8D-5LJN 65 GAL16LV8C-7LJN1 IC E 10 65 GAL16LV8C-10LJN 65 GAL16LV8C-15LJN Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC V U Discontinued per PCN Contact Rochester Electronics for available inventory. E IN Part Number Description _ XX X XX X L D NT GAL16LV8D Device Name GAL16LV8C L O Speed ns ADISC L= Low Power Grade Blank = Commercial Package J = PLCC JN = Lead-free PLCC Specifications GAL16LV8 Output Logic Macrocell OLMC The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. PAL Architectures Emulated by GAL16LV8 GAL16LV8 Global OLMC Mode 16R8 Registered There are three global OLMC configuration modes possible: 16R6 Registered simple, complex, and registered. Details of each of these modes 16R4 Registered are illustrated in the following pages. Two global bits, SYN and 16RP8 Registered AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individ- S ual architecture bits define all possible configurations in a GAL16LV8. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will E transparently set these architecture bits from the pin definitions, so D the user should not need to directly manipulate these architecture bits. IC E The following is a list of the PAL architectures that the GAL16LV8 can emulate. It also shows the OLMC mode under which the V U GAL16LV8 emulates the PAL architecture.

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Device Datasheet

June 2010

All Devices Discontinued!

Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet.

The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status.

Product Line GAL16LV8C GAL16LV8D
Ordering Part Number GAL16LV8C-7LJ GAL16LV8C-7LJN GAL16LV8C-10LJ GAL16LV8C-10LJN GAL16LV8C-15LJ GAL16LV8C-15LJN GAL16LV8D-3LJ GAL16LV8D-3LJN GAL16LV8D-5LJ GAL16LV8D-5LJN

Product Status

Reference PCN#06-07

Discontinued

PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone 503 268-8000 z FAX 503 268-8347 Internet:

LePAOaavpdact-kiliFaaorgbneelsee!

GAL16LV8

Low Voltage E2CMOS PLD Generic Array Logic

Functional Block Diagram
• HIGH PERFORMANCE TECHNOLOGY

I/CLK
ns Maximum Propagation Delay

Fmax = 250 MHz
ns Maximum from Clock Input to Data Output Advanced CMOS Technology
8 OLMC

I/O/Q
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE JEDEC-Compatible 3.3V Interface Standard 5V Compatible Inputs I/O Interfaces with Standard 5V TTL Devices

S GAL16LV8C
• ACTIVE PULL-UPS ON ALL PINS GAL16LV8D Only
• E2 CELL TECHNOLOGY

E D Reconfigurable Logic

Reprogrammable Cells 100% Tested/100% Yields

IC E High Speed Electrical Erasure <100ms
20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS Maximum Flexibility for Complex Logic Designs

V U Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS 100% Functional Testability

E IN
• APPLICATIONS INCLUDE Glue Logic for 3.3V Systems DMA Control State Machine Control D T High Speed Graphics Processing Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

L N
• LEAD-FREE PACKAGE OPTIONS

Pin Configuration

PROGRAMMABLE AND-ARRAY 64 X 32
8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC

I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/OE

L O The GAL16LV8D, at ns maximum propagation delay time,
provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V

A C signal levels. The GAL16LV8 is manufactured using Lattice

Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable E2 floating gate technology. High speed erase times <100ms allow the devices to be repro-

IS grammed quickly and efficiently.

The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features
GAL16LV8 Ordering Information

Conventional Packaging Commercial Grade Specifications

Tpd ns Tsu ns Tco ns Icc mA
Ordering #

Package
70 GAL16LV8D-3LJ
20-Lead PLCC
70 GAL16LV8D-5LJ
20-Lead PLCC
65 GAL16LV8C-7LJ1
20-Lead PLCC
65 GAL16LV8C-10LJ
65 GAL16LV8C-15LJ
20-Lead PLCC 20-Lead PLCC

Lead-Free Packaging

S Commercial Grade Specifications

Tpd ns Tsu ns Tco ns Icc mA
Ordering #

Package
70 GAL16LV8D-3LJN
70 GAL16LV8D-5LJN
65 GAL16LV8C-7LJN1

IC E 10
65 GAL16LV8C-10LJN
65 GAL16LV8C-15LJN

Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC Lead-Free 20-Lead PLCC

V U Discontinued per PCN Contact Rochester Electronics for available inventory.

E IN Part Number Description
_ XX X XX X

L D NT GAL16LV8D Device Name

GAL16LV8C

L O Speed ns ADISC L= Low Power

Grade Blank = Commercial

Package J = PLCC JN = Lead-free PLCC

Specifications GAL16LV8

Output Logic Macrocell OLMC

The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.

PAL Architectures Emulated by GAL16LV8

GAL16LV8 Global OLMC Mode
16R8

Registered

There are three global OLMC configuration modes possible:
16R6

Registered
simple, complex, and registered. Details of each of these modes
16R4

Registered
are illustrated in the following pages. Two global bits, SYN and
16RP8

Registered

AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individ-

S ual architecture bits define all possible configurations in a

GAL16LV8. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will

E transparently set these architecture bits from the pin definitions, so D the user should not need to directly manipulate these architecture
bits.

IC E The following is a list of the PAL architectures that the GAL16LV8
can emulate. It also shows the OLMC mode under which the

V U GAL16LV8 emulates the PAL architecture.

More datasheets: SL1122A200R | SL1122A090 | SL1122A450 | SL1122A230 | SL1122A200 | SL1122A260 | SL1122A090R | SL1122A350 | GAL16LV8C-10LJN | GAL16LV8C-15LJN

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived GAL16LV8D-3LJN Datasheet file may be downloaded here without warranties.

Datasheet ID: GAL16LV8D-3LJN 645468