LFE3-95E-8FN672C

LFE3-95E-8FN672C Datasheet

LFE3 XXX XX X

Part	Datasheet
LFE3-95E-8FN672C	LFE3-95E-8FN672C (pdf)

Related Parts	Information
LFE3-95E-7FN484I	LFE3-95E-7FN484I
LFE3-95E-8FN484C	LFE3-95E-8FN484C
LFE3-95E-8FN484I	LFE3-95E-8FN484I
LFE3-95E-6FN1156C	LFE3-95E-6FN1156C
LFE3-70E-6FN672I	LFE3-70E-6FN672I
LFE3-95E-7FN672I	LFE3-95E-7FN672I
LFE3-95E-8FN1156C	LFE3-95E-8FN1156C
LFE3-95E-8FN1156I	LFE3-95E-8FN1156I
LFE3-70E-6FN1156C	LFE3-70E-6FN1156C
LFE3-70E-6FN1156I	LFE3-70E-6FN1156I
LFE3-70E-6FN484C	LFE3-70E-6FN484C
LFE3-95E-7FN672C	LFE3-95E-7FN672C
LFE3-70E-6FN484I	LFE3-70E-6FN484I
LFE3-70E-7FN1156C	LFE3-70E-7FN1156C
LFE3-70E-7FN672I	LFE3-70E-7FN672I
LFE3-70E-8FN672I	LFE3-70E-8FN672I
LFE3-70E-7FN1156I	LFE3-70E-7FN1156I
LFE3-70E-7FN484C	LFE3-70E-7FN484C
LFE3-70E-7FN672C	LFE3-70E-7FN672C
LFE3-70E-8FN1156C	LFE3-70E-8FN1156C
LFE3-70E-8FN1156I	LFE3-70E-8FN1156I
LFE3-70E-8FN484C	LFE3-70E-8FN484C
LFE3-70E-8FN484I	LFE3-70E-8FN484I
LFE3-70E-8FN672C	LFE3-70E-8FN672C
LFE3-70E-6FN672C	LFE3-70E-6FN672C
LFE3-95E-8FN672I	LFE3-95E-8FN672I
LFE3-95E-6FN672C	LFE3-95E-6FN672C
LFE3-95E-7FN1156C	LFE3-95E-7FN1156C
LFE3-95E-7FN1156I	LFE3-95E-7FN1156I
LFE3-95E-6FN1156I	LFE3-95E-6FN1156I
LFE3-95E-6FN672I	LFE3-95E-6FN672I
LFE3-95E-7FN484C	LFE3-95E-7FN484C
LFE3-95E-6FN484C	LFE3-95E-6FN484C
LFE3-70E-7FN484I	LFE3-70E-7FN484I
LFE3-95E-6FN484I	LFE3-95E-6FN484I

PDF Datasheet Preview
A LatticeECP3 Family Data Sheet Preliminary DS1021 Version March 2010 LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 • Dedicated read/write levelling functionality Higher Logic Density for Increased System • Dedicated gearing logic • Source synchronous standards support Integration ADC/DAC, 7:1 LVDS, XGMII • 17K to 149K LUTs High Speed ADC/DAC devices • 133 to 586 I/Os Embedded SERDES • 150 Mbps to Gbps for Generic 8b10b, 10-bit A SERDES, and 8-bit SERDES modes • Data Rates 230 Mbps to Gbps per channel E for all other protocols - N • Up to 16 channels per device PCI Express, 3 SONET/SDH, Ethernet 1GbE, SGMII, XAUI , P OR IO CPRI, SMPTE 3G and Serial RapidIO sysDSP • Fully cascadable slice architecture C F T • 12 to 160 slices for high performance multiply and accumulate E A • Powerful 54-bit ALU operations e T • Time Division Multiplexing MAC Sharing ic E M • Rounding and truncation • Each slice supports t E R Half 36x36, two 18x18 or four 9x9 multipliers Advanced 18x36 MAC and 18x18 Multiply- at H O Multiply-Accumulate MMAC operations Flexible Memory Resources L S F • Up to 6.85Mbits sysMEM Embedded Block RAM EBR E A IN • 36K to 303K bits distributed RAM sysCLOCK Analog PLLs and DLLs • Two DLLs and up to ten PLLs per device E T Pre-Engineered Source Synchronous I/O • DDR registers in I/O cells • Dedicated DDR/DDR2/DDR3 memory with DQS support • Optional Inter-Symbol Interference ISI  correction on outputs Programmable sysI/O Buffer Supports Wide Range of Interfaces • On-chip termination • Optional equalization filter on inputs • LVTTL and LVCMOS 33/25/18/15/12 • SSTL 33/25/18/15 I, II • HSTL15 I and HSTL18 I, II • PCI and Differential HSTL, SSTL • LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS Flexible Device Configuration • Dedicated bank for configuration I/Os • SPI boot flash interface • Dual-boot images supported • Slave SPI • TransFR I/O for simple field updates • Soft Error Detect embedded macro System Level Support S A N Table LatticeECP3 Family Selection Guide Device ECP3-17 LatticeECP3 Family Data Sheet Ordering Information March 2010 Preliminary Data Sheet DS1021 LatticeECP3 Part Number Description LFE3 XXX XX X Device Family Grade ECP3 LatticeECP3 FPGA + SERDES Logic Capacity 17 = 17K LUTs A 35 = 33K LUTs 70 = 67K LUTs E 95 = 92K LUTs - N 150 = 149K LUTs 3 R Supply Voltage P O IO E or EA= 1.2V Speed 6 = Slowest C F T 7 8 = Fastest C = Commercial I = Industrial Package FTN256 = 256-ball Lead-Free ftBGA FN484 = 484-ball Lead-Free fpBGA FN672 = 672-ball Lead-Free fpBGA FN1156 = 1156-ball Lead-Free fpBGA iceE ET MA Ordering Information LatticeECP3 devices have top-side markings, for commercial and industrial grades, as shown below: t E R Commercial Industrial at H O ECP3 L S F LFE3-95E 7FN672C SECEDUARTRAENT IN Datecode ECP3 LFE3-95E 7FN672I Datecode 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. DS1021 Order Info_01.2 Lattice Semiconductor Ordering Information LatticeECP3 Family Data Sheet LatticeECP3 Devices, Lead-Free Packaging The following devices may have associated errata. Specific devices with associated errata will be notated with a footnote. Commercial Voltage Grade Package Pins Temp. LUTs K LFE3-17EA-6FTN256C 1.2V Lead-Free ftBGA LFE3-17EA-7FTN256C 1.2V Lead-Free ftBGA LFE3-17EA-8FTN256C LFE3-17EA-6FN484C LFE3-17EA-7FN484C A LFE3-17EA-8FN484C 1.2V 1.2V 1.2V 1.2V Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA 3-E R N Part Number P O IO LFE3-35EA-6FTN256C LFE3-35EA-7FTN256C C F T LFE3-35EA-8FTN256C LFE3-35EA-6FN484C E A LFE3-35EA-7FN484C e T LFE3-35EA-8FN484C ic E M LFE3-35EA-6FN672C LFE3-35EA-7FN672C t E R LFE3-35EA-8FN672C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -6 -7 -8 -6 -7 -8 -6 -7 -8 Package Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 256 484 672 Temp. COM LUTs K 33 Lat SH FO Part Number LFE3-70EA-6FN484C E A IN LFE3-70EA-7FN484C LFE3-70EA-8FN484C E T LFE3-70EA-6FN672C Ordering Information LatticeECP3 Family Data Sheet Voltage Grade Package Pins Temp. LUTs K LFE3-70E-6FN484C1 1.2V Lead-Free fpBGA LFE3-70E-7FN484C1 1.2V Lead-Free fpBGA LFE3-70E-8FN484C1 1.2V Lead-Free fpBGA LFE3-70E-6FN672C1 1.2V Lead-Free fpBGA LFE3-70E-7FN672C1 1.2V Lead-Free fpBGA LFE3-70E-8FN672C1 1.2V Lead-Free fpBGA LFE3-70E-6FN1156C1 1.2V Lead-Free fpBGA 1156 LFE3-70E-7FN1156C1 1.2V Lead-Free fpBGA 1156 A LFE3-70E-8FN1156C1 1.2V Lead-Free fpBGA 1156 1.This device has associated errata. View for a description of the errata. -E N Part Number 3 R LFE3-95EA-6FN484C P O IO LFE3-95EA-7FN484C LFE3-95EA-8FN484C C F T LFE3-95EA-6FN672C Ordering Information LatticeECP3 Family Data Sheet Voltage Grade Package Pins Temp. LUTs K LFE3-150EA-6FN672CTW* 1.2V Lead-Free fpBGA LFE3-150EA-7FN672CTW* 1.2V Lead-Free fpBGA LFE3-150EA-8FN672CTW* 1.2V Lead-Free fpBGA LFE3-150EA-6FN1156CTW* 1.2V Lead-Free fpBGA 1156 LFE3-150EA-7FN1156CTW* 1.2V Lead-Free fpBGA 1156 LFE3-150EA-8FN1156CTW* 1.2V Lead-Free fpBGA 1156 Note Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, where sp is the speed and A pkg is the package , are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as specified below. E • The CTC Clock Tolerance Circuit inside the SERDES hard PCS in the TW device is not functional but it can be - bypassed and implemented in soft IP. • Lattice Semiconductor Ordering Information LatticeECP3 Family Data Sheet Industrial The following devices may have associated errata. Specific devices with associated errata will be notated with a footnote. Voltage Grade Package Pins Temp. LUTs K LFE3-17EA-6FTN256I 1.2V Lead-Free ftBGA LFE3-17EA-7FTN256I 1.2V Lead-Free ftBGA LFE3-17EA-8FTN256I 1.2V Lead-Free ftBGA LFE3-17EA-6FN484I 1.2V Lead-Free fpBGA LFE3-17EA-7FN484I 1.2V Lead-Free fpBGA LFE3-17EA-8FN484I 1.2V Lead-Free fpBGA -EA N Part Number 3 LFE3-35EA-6FTN256I P OR IO LFE3-35EA-7FTN256I LFE3-35EA-8FTN256I C F T LFE3-35EA-6FN484I LFE3-35EA-7FN484I E A LFE3-35EA-8FN484I e T LFE3-35EA-6FN672I ic E M LFE3-35EA-7FN672I LFE3-35EA-8FN672I Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -6 -7 -8 -6 -7 -8 -6 -7 -7 Package Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 256 484 672 Temp. IND LUTs K 33 att HE OR Part Number L S F LFE3-70EA-6FN484I LFE3-70EA-7FN484I Ordering Information LatticeECP3 Family Data Sheet Voltage Grade Package Pins Temp. LUTs K LFE3-70E-6FN484I1 1.2V Lead-Free fpBGA LFE3-70E-7FN484I1 1.2V Lead-Free fpBGA LFE3-70E-8FN484I1 1.2V Lead-Free fpBGA LFE3-70E-6FN672I1 1.2V Lead-Free fpBGA LFE3-70E-7FN672I1 1.2V Lead-Free fpBGA LFE3-70E-8FN672I1 1.2V Lead-Free fpBGA LFE3-70E-6FN1156I1 1.2V Lead-Free fpBGA 1156 LFE3-70E-7FN1156I1 1.2V Lead-Free fpBGA 1156 A LFE3-70E-8FN1156I1 1.2V Lead-Free fpBGA 1156 1.This device has associated errata. View for a description of the errata. P3-EOR ION Part Number LFE3-95EA-6FN484I LFE3-95EA-7FN484I C F T LFE3-95EA-8FN484I E A LFE3-95EA-6FN672I e T LFE3-95EA-7FN672I ic E M LFE3-95EA-8FN672I Ordering Information LatticeECP3 Family Data Sheet Voltage Grade Package Pins Temp. LUTs K LFE3-150EA-6FN672I 1.2V Lead-Free fpBGA LFE3-150EA-7FN672I 1.2V Lead-Free fpBGA LFE3-150EA-8FN672I 1.2V Lead-Free fpBGA LFE3-150EA-6FN1156I 1.2V Lead-Free fpBGA 1156 LFE3-150EA-7FN1156I 1.2V Lead-Free fpBGA 1156 LFE3-150EA-8FN1156I 1.2V Lead-Free fpBGA 1156 A Part Number E LFE3-150EA-6FN672ITW - N LFE3-150EA-7FN672ITW* 3 LFE3-150EA-8FN672ITW* P OR IO LFE3-150EA-6FN1156ITW* LFE3-150EA-7FN1156ITW* C F T LFE3-150EA-8FN1156ITW* Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -6 -7 -8 -6 -7 -8 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 1156 Temp. IND LUTs K 149 E A *Note Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, where sp is the speed and e T pkg is the package , are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as specified below. ic E M • The CTC Clock Tolerance Circuit inside the SERDES hard PCS in the TW device is not functional but it can be bypassed and implemented in soft IP. SECEDULARaTRttAENSHT EINFOR • The SERDES XRES pin on the TW device passes CDM testing at 250V. Ordering Information Added LFE3-150EA “TW” devices and footnotes to the Commercial and Industrial tables. Architecture Added Read-Before-Write information. DC and Switching Characteristics Added footnote #6 to Maximum I/O Buffer Speed table. Corrected minimum operating conditions for input and output differential voltages in the Point-to-Point LVDS table. Pinout Information Added pin information for the LatticeECP3-70EA and LatticeECP395EA devices. Ordering Information Added ordering part numbers for the LatticeECP3-70EA and LatticeECP3-95EA devices. Removed dual mark information.

PDF Datasheet Preview

A LatticeECP3 Family Data Sheet Preliminary DS1021 Version March 2010

LatticeECP3 Family Data Sheet Introduction

November 2009

Preliminary Data Sheet DS1021
• Dedicated read/write levelling functionality

Higher Logic Density for Increased System
• Dedicated gearing logic
• Source synchronous standards support

Integration

ADC/DAC, 7:1 LVDS, XGMII
• 17K to 149K LUTs

High Speed ADC/DAC devices
• 133 to 586 I/Os

Embedded SERDES
• 150 Mbps to Gbps for Generic 8b10b, 10-bit

A SERDES, and 8-bit SERDES modes
• Data Rates 230 Mbps to Gbps per channel

E for all other protocols - N
• Up to 16 channels per device PCI Express, 3 SONET/SDH, Ethernet 1GbE, SGMII, XAUI , P OR IO CPRI, SMPTE 3G and Serial RapidIO
sysDSP
• Fully cascadable slice architecture

C F T
• 12 to 160 slices for high performance multiply and accumulate

E A
• Powerful 54-bit ALU operations e T
• Time Division Multiplexing MAC Sharing ic E M
• Rounding and truncation
• Each slice supports
t E R Half 36x36, two 18x18 or four 9x9 multipliers

Advanced 18x36 MAC and 18x18 Multiply-
at H O Multiply-Accumulate MMAC operations

Flexible Memory Resources

L S F
• Up to 6.85Mbits sysMEM Embedded Block RAM EBR

E A IN
• 36K to 303K bits distributed RAM
sysCLOCK Analog PLLs and DLLs
• Two DLLs and up to ten PLLs per device

E T Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated DDR/DDR2/DDR3 memory with DQS support
• Optional Inter-Symbol Interference ISI  correction on outputs

Programmable sysI/O Buffer Supports Wide Range of Interfaces
• On-chip termination
• Optional equalization filter on inputs
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 33/25/18/15 I, II
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

Flexible Device Configuration
• Dedicated bank for configuration I/Os
• SPI boot flash interface
• Dual-boot images supported
• Slave SPI
• TransFR I/O for simple field updates
• Soft Error Detect embedded macro

System Level Support

S A N Table LatticeECP3 Family Selection Guide

Device

ECP3-17
LatticeECP3 Family Data Sheet Ordering Information

March 2010

Preliminary Data Sheet DS1021

LatticeECP3 Part Number Description

LFE3 XXX XX X

Device Family

Grade

ECP3 LatticeECP3 FPGA + SERDES

Logic Capacity 17 = 17K LUTs

A 35 = 33K LUTs
70 = 67K LUTs

E 95 = 92K LUTs - N 150 = 149K LUTs 3 R Supply Voltage P O IO E or EA= 1.2V

Speed 6 = Slowest

C F T 7
8 = Fastest

C = Commercial I = Industrial

Package FTN256 = 256-ball Lead-Free ftBGA FN484 = 484-ball Lead-Free fpBGA FN672 = 672-ball Lead-Free fpBGA FN1156 = 1156-ball Lead-Free fpBGA
iceE ET MA Ordering Information

LatticeECP3 devices have top-side markings, for commercial and industrial grades, as shown below:
t E R Commercial

Industrial
at H O ECP3 L S F LFE3-95E
7FN672C

SECEDUARTRAENT IN Datecode

ECP3 LFE3-95E 7FN672I

Datecode
2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

DS1021 Order Info_01.2

Lattice Semiconductor
Ordering Information LatticeECP3 Family Data Sheet

LatticeECP3 Devices, Lead-Free Packaging

The following devices may have associated errata. Specific devices with associated errata will be notated with a footnote.

Commercial

Voltage

Grade

Package

Pins

Temp.

LUTs K

LFE3-17EA-6FTN256C
1.2V

Lead-Free ftBGA

LFE3-17EA-7FTN256C
1.2V

Lead-Free ftBGA

LFE3-17EA-8FTN256C LFE3-17EA-6FN484C LFE3-17EA-7FN484C

A LFE3-17EA-8FN484C
1.2V 1.2V 1.2V 1.2V

Lead-Free ftBGA

Lead-Free fpBGA

Lead-Free fpBGA

Lead-Free fpBGA
3-E R N Part Number P O IO LFE3-35EA-6FTN256C

LFE3-35EA-7FTN256C

C F T LFE3-35EA-8FTN256C

LFE3-35EA-6FN484C

E A LFE3-35EA-7FN484C e T LFE3-35EA-8FN484C ic E M LFE3-35EA-6FN672C

LFE3-35EA-7FN672C
t E R LFE3-35EA-8FN672C

Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V

Grade -6 -7 -8 -6 -7 -8 -6 -7 -8

Package Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA

Pins 256 484 672

Temp. COM

LUTs K 33

Lat SH FO Part Number

LFE3-70EA-6FN484C

E A IN LFE3-70EA-7FN484C

LFE3-70EA-8FN484C

E T LFE3-70EA-6FN672C
Ordering Information LatticeECP3 Family Data Sheet

Voltage

Grade

Package

Pins

Temp.

LUTs K

LFE3-70E-6FN484C1
1.2V

Lead-Free fpBGA

LFE3-70E-7FN484C1
1.2V

Lead-Free fpBGA

LFE3-70E-8FN484C1
1.2V

Lead-Free fpBGA

LFE3-70E-6FN672C1
1.2V

Lead-Free fpBGA

LFE3-70E-7FN672C1
1.2V

Lead-Free fpBGA

LFE3-70E-8FN672C1
1.2V

Lead-Free fpBGA

LFE3-70E-6FN1156C1
1.2V

Lead-Free fpBGA
1156

LFE3-70E-7FN1156C1
1.2V

Lead-Free fpBGA
1156

A LFE3-70E-8FN1156C1
1.2V

Lead-Free fpBGA
1156
1.This device has associated errata. View for a description of the errata.
-E N Part Number 3 R LFE3-95EA-6FN484C P O IO LFE3-95EA-7FN484C

LFE3-95EA-8FN484C

C F T LFE3-95EA-6FN672C
Ordering Information LatticeECP3 Family Data Sheet

Voltage

Grade

Package

Pins

Temp. LUTs K

LFE3-150EA-6FN672CTW*
1.2V

Lead-Free fpBGA

LFE3-150EA-7FN672CTW*
1.2V

Lead-Free fpBGA

LFE3-150EA-8FN672CTW*
1.2V

Lead-Free fpBGA

LFE3-150EA-6FN1156CTW*
1.2V

Lead-Free fpBGA
1156

LFE3-150EA-7FN1156CTW*
1.2V

Lead-Free fpBGA
1156

LFE3-150EA-8FN1156CTW*
1.2V

Lead-Free fpBGA
1156
*Note Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, where sp is the speed and

A pkg is the package , are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as
specified below.

E
• The CTC Clock Tolerance Circuit inside the SERDES hard PCS in the TW device is not functional but it can be - bypassed and implemented in soft IP.
•

Lattice Semiconductor
Ordering Information LatticeECP3 Family Data Sheet

Industrial

The following devices may have associated errata. Specific devices with associated errata will be notated with a footnote.

Voltage

Grade

Package

Pins

Temp.

LUTs K

LFE3-17EA-6FTN256I
1.2V

Lead-Free ftBGA

LFE3-17EA-7FTN256I
1.2V

Lead-Free ftBGA

LFE3-17EA-8FTN256I
1.2V

Lead-Free ftBGA

LFE3-17EA-6FN484I
1.2V

Lead-Free fpBGA

LFE3-17EA-7FN484I
1.2V

Lead-Free fpBGA

LFE3-17EA-8FN484I
1.2V

Lead-Free fpBGA
-EA N Part Number 3 LFE3-35EA-6FTN256I P OR IO LFE3-35EA-7FTN256I

LFE3-35EA-8FTN256I

C F T LFE3-35EA-6FN484I

LFE3-35EA-7FN484I

E A LFE3-35EA-8FN484I e T LFE3-35EA-6FN672I ic E M LFE3-35EA-7FN672I

LFE3-35EA-8FN672I

Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V

Grade -6 -7 -8 -6 -7 -8 -6 -7 -7

Package Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA

Pins 256 484 672

Temp. IND

LUTs K 33
att HE OR Part Number L S F LFE3-70EA-6FN484I

LFE3-70EA-7FN484I
Ordering Information LatticeECP3 Family Data Sheet

Voltage

Grade

Package

Pins

Temp.

LUTs K

LFE3-70E-6FN484I1
1.2V

Lead-Free fpBGA

LFE3-70E-7FN484I1
1.2V

Lead-Free fpBGA

LFE3-70E-8FN484I1
1.2V

Lead-Free fpBGA

LFE3-70E-6FN672I1
1.2V

Lead-Free fpBGA

LFE3-70E-7FN672I1
1.2V

Lead-Free fpBGA

LFE3-70E-8FN672I1
1.2V

Lead-Free fpBGA

LFE3-70E-6FN1156I1
1.2V

Lead-Free fpBGA
1156

LFE3-70E-7FN1156I1
1.2V

Lead-Free fpBGA
1156

A LFE3-70E-8FN1156I1
1.2V

Lead-Free fpBGA
1156
1.This device has associated errata. View for a description of the errata.

P3-EOR ION Part Number

LFE3-95EA-6FN484I LFE3-95EA-7FN484I

C F T LFE3-95EA-8FN484I E A LFE3-95EA-6FN672I e T LFE3-95EA-7FN672I ic E M LFE3-95EA-8FN672I
Ordering Information LatticeECP3 Family Data Sheet

Voltage

Grade

Package

Pins

Temp.

LUTs K

LFE3-150EA-6FN672I
1.2V

Lead-Free fpBGA

LFE3-150EA-7FN672I
1.2V

Lead-Free fpBGA

LFE3-150EA-8FN672I
1.2V

Lead-Free fpBGA

LFE3-150EA-6FN1156I
1.2V

Lead-Free fpBGA
1156

LFE3-150EA-7FN1156I
1.2V

Lead-Free fpBGA
1156

LFE3-150EA-8FN1156I
1.2V

Lead-Free fpBGA
1156

A Part Number E LFE3-150EA-6FN672ITW* - N LFE3-150EA-7FN672ITW* 3 LFE3-150EA-8FN672ITW* P OR IO LFE3-150EA-6FN1156ITW*

LFE3-150EA-7FN1156ITW*

C F T LFE3-150EA-8FN1156ITW*

Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V

Grade -6 -7 -8 -6 -7 -8

Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA

Pins 672 1156

Temp. IND

LUTs K 149

E A *Note Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, where sp is the speed and e T pkg is the package , are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as
specified below.
ic E M
• The CTC Clock Tolerance Circuit inside the SERDES hard PCS in the TW device is not functional but it can be bypassed and implemented in soft IP.

SECEDULARaTRttAENSHT EINFOR
• The SERDES XRES pin on the TW device passes CDM testing at 250V.
Ordering Information Added LFE3-150EA “TW” devices and footnotes to the Commercial and Industrial tables.

Architecture

Added Read-Before-Write information.

DC and Switching Characteristics

Added footnote #6 to Maximum I/O Buffer Speed table.

Corrected minimum operating conditions for input and output differential voltages in the Point-to-Point LVDS table.

Pinout Information Added pin information for the LatticeECP3-70EA and LatticeECP395EA devices.
Ordering Information Added ordering part numbers for the LatticeECP3-70EA and LatticeECP3-95EA devices.

Removed dual mark information.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived LFE3-95E-8FN672C Datasheet file may be downloaded here without warranties.

Datasheet ID: LFE3-95E-8FN672C 645463