DMA-MC-SC-N3

DMA-MC-SC-N3 Datasheet

Multi-channel DMA Controller

Part	Datasheet
DMA-MC-SC-N3	DMA-MC-SC-N3 (pdf)

Related Parts	Information
DMA-MC-XM-N3	DMA-MC-XM-N3
DMA-MC-E2-N3	DMA-MC-E2-N3
DMA-MC-O4-N2	DMA-MC-O4-N2
DMA-MC-XP-N2	DMA-MC-XP-N2

PDF Datasheet Preview
Multi-channel DMA Controller Home > Products > Intellectual Property > Lattice IP Cores > Multi-channel DMA Controller Multi-channel DMA Controller Overview The Multi-Channel Direct Memory Access MCDMA Controller is designed to improve microprocessor system performance by allowing external devices to directly transfer information from the system memory. Memory-tomemory transfer capability is also supported. The MCDMA Controller core supports two modes 8237 and non-8237. When the 8237 mode is selected, it configures the core to be compatible with the Intel 8237A DMA Controller with a few variations. These variations are listed in the "Compatibility Differences with the 8237 Intel Device" section of the datasheet. The 8237 mode supports four independent channels while the non-8237 mode supports up to 16 independent channels. Selectable 8237 Mode Configurable up to 16 Independent DMA Channels for Non-8237 Mode Configurable Data Width of 8, 16, 32 or 64 Bits for Non-8237 Mode Configurable Address Width of 16, 24 or 32 Bits for Non-8237 Mode Configurable Word Count Register Width for Non-8237 Mode Independent Auto-initialization of All Channels Memory-to-Memory Transfers on Single, Block, and Demand Transfer Modes Memory Block Initialization Software DMA Requests Evaluation Configurations Evaluation Configurations Available for Series 4 ORCA FPGAs and FPSCs1 Name of Parameter File dma_mc_o4_2_001.lpc dma_mc_o4_2_002.lpc 10/11/2011 Multi-channel DMA Controller Mode LUTs ORCA4 PFUs2 Registers SysMem EBR External Pins fMAX MHz # of Channels Data Bus Width Address Bus Width Word Count Width 8237 1258 524 N/A 59 58 4 8 16 Non-8237 2661 499 1187 N/A 125 66 4 32 16 1 Performance and utilization characteristics are generated using OR4E02-2PBGAM680-DE in Lattice’s ispLEVERTM v3.0 SP1 software. Synthesized using Synplicity Synplify v.7.03. When using this IP core in a different density, package, speed, or grade within the ORCA family, performance may vary slightly. 2 PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device. Please contact your local Lattice sales office to obtain other evaluation configurations. Evaluation Configurations Available for ispXPGA1 Name of Parameter File dma_mc_xp_2_001.lpc dma_mc_xp_2_002.lpc Mode 8237 Non-8237 LUT42 1450 3487 ispXPGA PFUs2 1072 Registers 1181 SysMem EBRs External Pins fMAX MHz # of Channels Data Bus Width Address Bus Width Ordering Information Part Numbers For ORCA 4 DMA-MC-O4-N2 For ispXPGA DMA-MC-XP-N2 For LatticeECP/EC DMA-MC-E2-N3 For LatticeXP DMA-MC-XM-N3 For LatticeSC DMA-MC-SC-N3 To find out how to purchase the Multi-channel DMA Controller IP Core, please contact your local Lattice Sales Office. 10/11/2011

PDF Datasheet Preview

Multi-channel DMA Controller

Home > Products > Intellectual Property > Lattice IP Cores > Multi-channel DMA Controller

Multi-channel DMA Controller

Overview

The Multi-Channel Direct Memory Access MCDMA Controller is designed to improve microprocessor system performance by allowing external devices to directly transfer information from the system memory. Memory-tomemory transfer capability is also supported.

The MCDMA Controller core supports two modes 8237 and non-8237. When the 8237 mode is selected, it configures the core to be compatible with the Intel 8237A DMA Controller with a few variations. These variations are listed in the "Compatibility Differences with the 8237 Intel Device" section of the datasheet. The 8237 mode supports four independent channels while the non-8237 mode supports up to 16 independent channels.

Selectable 8237 Mode Configurable up to 16 Independent DMA Channels for Non-8237 Mode Configurable Data Width of 8, 16, 32 or 64 Bits for Non-8237 Mode Configurable Address Width of 16, 24 or 32 Bits for Non-8237 Mode Configurable Word Count Register Width for Non-8237 Mode Independent Auto-initialization of All Channels Memory-to-Memory Transfers on Single, Block, and Demand Transfer Modes Memory Block Initialization Software DMA Requests

Evaluation Configurations

Evaluation Configurations Available for Series 4 ORCA FPGAs and FPSCs1

Name of Parameter File
dma_mc_o4_2_001.lpc dma_mc_o4_2_002.lpc
10/11/2011

Multi-channel DMA Controller

Mode LUTs ORCA4 PFUs2 Registers SysMem EBR External Pins fMAX MHz # of Channels Data Bus Width Address Bus Width Word Count Width
8237 1258
524 N/A
59 58
4 8 16

Non-8237 2661 499
1187 N/A 125 66 4 32 16
1 Performance and utilization characteristics are generated using OR4E02-2PBGAM680-DE in Lattice’s ispLEVERTM v3.0 SP1 software. Synthesized using Synplicity Synplify v.7.03. When using this IP core in a different density, package, speed, or grade within the ORCA family, performance may vary slightly. 2 PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.

Please contact your local Lattice sales office to obtain other evaluation configurations.

Evaluation Configurations Available for ispXPGA1

Name of Parameter File
dma_mc_xp_2_001.lpc dma_mc_xp_2_002.lpc

Mode
8237

Non-8237

LUT42
1450
3487
ispXPGA PFUs2
1072

Registers
1181

SysMem EBRs

External Pins
fMAX MHz
# of Channels

Data Bus Width

Address Bus Width
Ordering Information

Part Numbers For ORCA 4 DMA-MC-O4-N2 For ispXPGA DMA-MC-XP-N2 For LatticeECP/EC DMA-MC-E2-N3 For LatticeXP DMA-MC-XM-N3 For LatticeSC DMA-MC-SC-N3 To find out how to purchase the Multi-channel DMA Controller IP Core, please contact your local Lattice Sales Office.
10/11/2011

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DMA-MC-SC-N3 Datasheet file may be downloaded here without warranties.

Datasheet ID: DMA-MC-SC-N3 645461