M-8880-01T

M-8880-01T Datasheet

M-8880 DTMF Transceiver

Part	Datasheet
M-8880-01T	M-8880-01T (pdf)

Related Parts	Information
M-8880-01SM	M-8880-01SM
M-8880-01P	M-8880-01P

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M-8880 DTMF Transceiver • Advanced CMOS technology for low power consump- tion and increased noise immunity • Complete DTMF transmitter/receiver in a single chip • Standard 6500/6800 series microprocessor port • Central office quality and performance • Adjustable guard time • Automatic tone burst mode • Call progress mode • Single +5 Volt power supply • 20-pin DIP and SOIC packages • 2 MHz microprocessor port operation • Inexpensive MHz crystal • No continuous f2 clock required, only strobe • Applications include paging systems, repeater sys- tems/mobile radio, interconnect dialers, PBX systems, computer systems, fax machines, pay telephones, credit card verification The M-8880 is a complete DTMF Transmitter/Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 6500/6800 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for low-distortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor. Figure 1 Pin Diagram Functional Description M-8880 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 6500/6800 series microprocessor interface allows access to an internal status register, two control registers, and two data registers. Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources VREF for biasing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output GS for gain adjust- Figure 2 Block Diagram Page 1 M-8880 Figure 3 Single-Ended Input Configuration Figure 4 Differential Input Configuration ment. In a single-ended configuration, the input pins should be connected as shown in Figure 4 shows the necessary connections for a differential input configuration. Receiver Section The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in Table The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smooths the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming DTMF signal frequencies. A decoder employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice , while tolerating small deviations in frequency. The algorithm provides an optimum combination of immunity to talkoff with tolerance to interfering frequencies third tones and noise. When the detector recognizes the presence of two valid tones referred to as “signal condition” , the early steering ESt output goes to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state. Steering Circuit Before a decoded tone pair is registered, the receiver checks for a valid signal duration referred to as “character recognition condition” . This check is performed by an external RC time constant driven by ESt. A logic high on ESt Table 1 Pin Functions Name IN+ INGS VREF VSS OSC1 OSC2 TONE R/W CS RS0 IRQ/CP D0 - D3 ESt St/GT Noninverting op-amp input. Inverting op-amp input. Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail. Negative power supply input. DTMF clock/oscillator input. Clock output. A MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Dual tone multifrequency DTMF output. Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter. TTL compatible. Chip select. TTL input CS = 0 to select the chip . Register select input. See Table TTL compatible. System clock input. May be continuous or strobed only during read or write. TTL compatible. Interrupt request to microprocessor open-drain output . Also, when call progress CP mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11 Microprocessor data bus. TTL compatible. Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair signal condition . Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output bidirectional . A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant its state is a funciton of ESt and the voltage on St. Positive power supply input. M-8880 causes VC see Figure 5 to rise as the capacitor discharges. Provided that the signal condition is maintained ESt remains high for the validation period tGTP , VC reaches the threshold VTSt of the steering logic to register the tone pair, latching its corresponding 4-bit code see Table 2 into the receive data reg- ister. Table 2 Tone Encoding/Decoding FLOW FHIGH Digit 697 1209 697 1336 697 1477 770 1209 770 1336 770 1477 852 1209 852 1336 Ordering Information M-888001P M-8880-01SM M-8880-01T 20-pin plastic DIP 20-pin plastic SOIC 20-pin plastic SOIC,Tape and Reel Figure 9 Equations Table 6 Internal Register Functions Function Write to transmitter Read from receiver Write to control register Read from status register b3 RSEL Table 7 CRA Bit Postions CP/DTMF b0 TOUT Table 8 CRB Bit Positions TEST BURST Figure 10 Application Circuit Single-Ended Input Page 6 M-8880 Table 9 Status Register Description Name Status Flag Set Status Flag Cleared b0 IRQ Interrupt has occurred. Bi tone b1 and/or bit 2 b2 Interrupt is inactive. Cleared after status register is is set. read. b1 Transmit data register Pause duration has terminated and transmitter is empty burst mode only ready for new data. Cleared after status register is read or when not in burst mode. b2 Receive data register full Valid data is in the receive data register. Cleared after status register is read. b3 Delayed steering Set on valid detection of the absence of a DTMF sig- Cleared on detection of a valid DTMF signal. nal. Table 10 Absolute Maximum Ratings Parameter Value Power supply voltage VDD - VSS + V max Voltage on any pin

PDF Datasheet Preview

M-8880 DTMF Transceiver
• Advanced CMOS technology for low power consump-
tion and increased noise immunity
• Complete DTMF transmitter/receiver in a single chip
• Standard 6500/6800 series microprocessor port
• Central office quality and performance
• Adjustable guard time
• Automatic tone burst mode
• Call progress mode
• Single +5 Volt power supply
• 20-pin DIP and SOIC packages
• 2 MHz microprocessor port operation
• Inexpensive MHz crystal
• No continuous f2 clock required, only strobe
• Applications include paging systems, repeater sys-
tems/mobile radio, interconnect dialers, PBX systems, computer systems, fax machines, pay telephones, credit card verification

The M-8880 is a complete DTMF Transmitter/Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 6500/6800 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for low-distortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor.

Figure 1 Pin Diagram

Functional Description

M-8880 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 6500/6800 series microprocessor interface allows access to an internal status register, two control registers, and two data registers.

Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources VREF for biasing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output GS for gain adjust-

Figure 2 Block Diagram Page 1

M-8880

Figure 3 Single-Ended Input Configuration

Figure 4 Differential Input Configuration
ment. In a single-ended configuration, the input pins should be connected as shown in Figure 4 shows the necessary connections for a differential input configuration.

Receiver Section

The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in Table The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smooths the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming DTMF signal frequencies.

A decoder employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice , while tolerating small deviations in frequency. The algorithm provides an optimum combination of immunity to talkoff with tolerance to interfering frequencies third tones and noise. When the detector recognizes the presence of two valid tones referred to as “signal condition” , the early steering ESt output goes to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.

Steering Circuit Before a decoded tone pair is registered, the receiver checks for a valid signal duration referred to as “character recognition condition” . This check is performed by an external RC time constant driven by ESt. A logic high on ESt

Table 1 Pin Functions

Name IN+ INGS VREF VSS

OSC1 OSC2 TONE R/W

CS RS0 IRQ/CP

D0 - D3 ESt

St/GT

Noninverting op-amp input. Inverting op-amp input. Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail. Negative power supply input. DTMF clock/oscillator input. Clock output. A MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Dual tone multifrequency DTMF output. Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter. TTL compatible. Chip select. TTL input CS = 0 to select the chip . Register select input. See Table TTL compatible. System clock input. May be continuous or strobed only during read or write. TTL compatible.

Interrupt request to microprocessor open-drain output . Also, when call progress CP mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11 Microprocessor data bus. TTL compatible. Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair signal condition . Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output bidirectional . A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant its state is a funciton of ESt and the voltage on St. Positive power supply input.

M-8880
causes VC see Figure 5 to rise as the capacitor discharges. Provided that the signal condition is maintained ESt remains
high for the validation period tGTP , VC reaches the threshold VTSt of the steering logic to register the tone pair, latching its corresponding 4-bit code see Table 2 into the receive data reg-
ister.

Table 2 Tone Encoding/Decoding

FLOW FHIGH Digit
697 1209
697 1336
697 1477
770 1209
770 1336
770 1477
852 1209
852 1336
Ordering Information

M-888001P M-8880-01SM M-8880-01T
20-pin plastic DIP 20-pin plastic SOIC 20-pin plastic SOIC,Tape and Reel

Figure 9 Equations

Table 6 Internal Register Functions

Function

Write to transmitter

Read from receiver

Write to control register

Read from status register
b3 RSEL

Table 7 CRA Bit Postions

CP/DTMF
b0 TOUT

Table 8 CRB Bit Positions

TEST

BURST

Figure 10 Application Circuit Single-Ended Input

Page 6

M-8880

Table 9 Status Register Description

Name

Status Flag Set

Status Flag Cleared
b0 IRQ

Interrupt has occurred. Bi tone b1 and/or bit 2 b2 Interrupt is inactive. Cleared after status register is
is set.
read.
b1 Transmit data register Pause duration has terminated and transmitter is empty burst mode only ready for new data.

Cleared after status register is read or when not in burst mode.
b2 Receive data register full

Valid data is in the receive data register.

Cleared after status register is read.
b3 Delayed steering

Set on valid detection of the absence of a DTMF sig- Cleared on detection of a valid DTMF signal. nal.

Table 10 Absolute Maximum Ratings

Parameter

Value

Power supply voltage VDD - VSS
+ V max

Voltage on any pin

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Datasheet ID: M-8880-01T 523331