X4325S8-4.5A

X4325S8-4.5A Datasheet

X4323, X4325

Part	Datasheet
X4325S8-4.5A	X4325S8-4.5A (pdf)

Related Parts	Information
X4323S8-2.7	X4323S8-2.7
X4323S8I-2.7	X4323S8I-2.7
X4323S8I	X4323S8I
X4323S8	X4323S8
X4325V8I-2.7A	X4325V8I-2.7A
X4325S8I	X4325S8I
X4325S8I-2.7A	X4325S8I-2.7A
X4325S8I-4.5A	X4325S8I-4.5A
X4325V8	X4325V8
X4323V8-4.5A	X4323V8-4.5A
X4325S8-2.7A	X4325S8-2.7A
X4323V8-2.7A	X4323V8-2.7A
X4325V8I-2.7	X4325V8I-2.7
X4323V8-2.7	X4323V8-2.7
X4325V8-2.7A	X4325V8-2.7A
X4325V8-4.5A	X4325V8-4.5A
X4325S8	X4325S8
X4325V8I	X4325V8I
X4325V8-2.7	X4325V8-2.7
X4323S8-4.5A	X4323S8-4.5A
X4325V8I-4.5A	X4325V8I-4.5A
X4323V8I-2.7	X4323V8I-2.7
X4323V8I	X4323V8I
X4323V8I-2.7A	X4323V8I-2.7A
X4323V8	X4323V8
X4323S8-2.7A	X4323S8-2.7A
X4323V8I-4.5A	X4323V8I-4.5A
X4325S8I-2.7	X4325S8I-2.7
X4323S8I-4.5A	X4323S8I-4.5A
X4323S8I-2.7A	X4323S8I-2.7A
X4325S8-2.7	X4325S8-2.7

PDF Datasheet Preview
Data Sheet X4323, X4325 32k, 4k x 8 Bit May 25, 2006 FN8122.1 CPU Supervisor with 32k EEPROM • Selectable watchdog timer • Low VCC detection and reset assertion standard reset threshold voltages low VCC reset threshold voltage using special programming sequence signal valid to VCC = 1V • Low power CMOS max standby current, watchdog on standby current, watchdog off active current • 32Kbits of EEPROM page write mode write cycle write cycle time typical • Built-in inadvertent write protection circuitry Lock 1, 2, 4, 8 pages, all, none • 400kHz 2-wire interface • 2.7V to 5.5V power supply operation • Available packages Ld SOIC Ld TSSOP • Pb-free plus anneal available RoHS compliant BLOCK DIAGRAM The X4323, X4325 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the set minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. WP SDA SCL S0 S1 Block Lock Control 4kb Watchdog Transition Detector Protect Logic Data Register Command Decode & Control Logic VCC Threshold Reset logic Status Register EEPROM Array VTRIP Watchdog Timer Reset Reset & Watchdog Timebase Power-on and Low Voltage Reset Generation RESET X4323 RESET X4325 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 \| Intersil and design is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. All Rights Reserved All other trademarks mentioned are the property of their respective owners. PIN CONFIGURATION X4323, X4325 8-Pin JEDEC SOIC S0 1 S1 2 RST/RST 3 VSS 4 8 VCC 7 WP 6 SCL Ordering Information PART NUMBER RESET ACTIVE LOW PART MARKING RESET PART VCC RANGE VTRIP RANGE TEMP. ACTIVE HIGH MARKING RANGE °C PACKAGE PKG. DWG. # X4323S8-2.7 X4323 F X4325S8-2.7 X4325 F 0 to 70 8 Ld SOIC 150 mil MDP0027 X4323S8Z-2.7 Note X4323S8I-2.7 X4323 ZF X4323 G X4325S8Z-2.7 Note X4325S8I-2.7 X4325 ZF X4325 G 0 to 70 -40 to 85 8 Ld SOIC 150 mil MDP0027 Pb-free 8 Ld SOIC 150 mil MDP0027 X4323S8IZ-2.7 X4323 ZG Note X4323V8-2.7 4323 F X4325S8IZ-2.7 X4325 ZG Note X4325V8-2.7 4325 F -40 to 85 0 to 70 8 Ld SOIC 150 mil MDP0027 Pb-free 8 Ld TSSOP 4.4mm M8.173 X4323V8Z-2.7 4323 FZ Note X4323V8I-2.7 4323 G X4323V8IZ-2.7 4323 GZ Note X4325V8Z-2.7 4325 FZ Note X4325V8I-2.7 4325 G X4325V8IZ-2.7 4325 GZ Note 0 to 70 -40 to 85 -40 to 85 8 Ld TSSOP 4.4mm M8.173 Pb-free 8 Ld TSSOP 4.4mm M8.173 8 Ld TSSOP 4.4mm M8.173 Pb-free X4323S8-2.7A X4323 AN Ordering Information Continued PART NUMBER RESET ACTIVE LOW PART MARKING RESET PART VCC RANGE VTRIP RANGE TEMP. ACTIVE HIGH MARKING RANGE °C PACKAGE PKG. DWG. # X4323V8-4.5A 4323 AL X4325V8-4.5A 4325 AL 0 to 70 8 Ld TSSOP 4.4mm M8.173 X4323V8Z-4.5A 4323 ALZ Note X4325V8Z-4.5A 4325 ALZ Note 0 to 70 8 Ld TSSOP 4.4mm M8.173 Pb-free X4323V8I-4.5A 4323 AM X4325V8I-4.5A 4325 AM -40 to 85 8 Ld TSSOP 4.4mm M8.173 X4323V8IZ-4.5A 4323 AMZ Note X4325V8IZ-4.5A 4325 AMZ Note -40 to 85 8 Ld TSSOP 4.4mm M8.173 Pb-free NOTE Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8122.1 May 25, 2006 X4323, X4325 PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4323, X4325 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. It prevents the system microprocessor from starting to operate with insufficient voltage. It prevents the processor from operating prior to stabilization of the oscillator. It allows time for an FPGA to download its configuration prior to initialization of the circuit. It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When VCC exceeds the device VTRIP threshold value for 200ms nominal the circuit releases RESET/RESET allowing the system to begin operation. LOW VOLTAGE MONITORING During operation, the X4323, X4325 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL is HIGH this is a start bit prior to the expiration of the watchdog time out period to prevent a RESET/RESET signal. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH. EEPROM INADVERTENT WRITE PROTECTION When RESET/RESET goes active as a result of a low voltage condition or Watchdog Timer Time Out, any inprogress communications are terminated. While RESET/RESET is active, no new communications are allowed and no nonvolatile write operation can start. Nonvolatile writes in-progress when RESET/RESET goes active are allowed to finish. Additional protection mechanisms are provided with memory Block Lock and the Write Protect WP pin. These are discussed elsewhere in this document.

PDF Datasheet Preview

Data Sheet

X4323, X4325
32k, 4k x 8 Bit

May 25, 2006

FN8122.1

CPU Supervisor with 32k EEPROM
• Selectable watchdog timer
• Low VCC detection and reset assertion
standard reset threshold voltages low VCC reset threshold voltage using
special programming sequence signal valid to VCC = 1V
• Low power CMOS max standby current, watchdog on standby current, watchdog off active current
• 32Kbits of EEPROM page write mode write cycle write cycle time typical
• Built-in inadvertent write protection circuitry Lock 1, 2, 4, 8 pages, all, none
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages Ld SOIC Ld TSSOP
• Pb-free plus anneal available RoHS compliant

BLOCK DIAGRAM

The X4323, X4325 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the set minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.

WP SDA SCL

S0 S1

Block Lock Control 4kb

Watchdog Transition Detector

Protect Logic

Data Register

Command Decode & Control

Logic

VCC Threshold Reset logic

Status Register

EEPROM Array

VTRIP

Watchdog Timer Reset

Reset & Watchdog Timebase

Power-on and Low Voltage

Reset Generation

RESET X4323 RESET X4325

CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil and design is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

PIN CONFIGURATION

X4323, X4325
8-Pin JEDEC SOIC

S0 1 S1 2 RST/RST 3

VSS 4
8 VCC 7 WP 6 SCL
Ordering Information

PART NUMBER RESET

ACTIVE LOW

PART MARKING

RESET

PART VCC RANGE VTRIP RANGE TEMP.

ACTIVE HIGH MARKING

RANGE °C

PACKAGE

PKG. DWG. #

X4323S8-2.7 X4323 F

X4325S8-2.7 X4325 F
0 to 70 8 Ld SOIC 150 mil MDP0027

X4323S8Z-2.7 Note

X4323S8I-2.7

X4323 ZF X4323 G

X4325S8Z-2.7 Note

X4325S8I-2.7

X4325 ZF X4325 G
0 to 70 -40 to 85
8 Ld SOIC 150 mil MDP0027 Pb-free
8 Ld SOIC 150 mil MDP0027

X4323S8IZ-2.7 X4323 ZG Note

X4323V8-2.7 4323 F

X4325S8IZ-2.7 X4325 ZG Note

X4325V8-2.7 4325 F
-40 to 85 0 to 70
8 Ld SOIC 150 mil MDP0027 Pb-free
8 Ld TSSOP 4.4mm M8.173

X4323V8Z-2.7 4323 FZ Note

X4323V8I-2.7 4323 G

X4323V8IZ-2.7 4323 GZ Note

X4325V8Z-2.7 4325 FZ Note

X4325V8I-2.7 4325 G

X4325V8IZ-2.7 4325 GZ Note
0 to 70
-40 to 85 -40 to 85
8 Ld TSSOP 4.4mm M8.173 Pb-free
8 Ld TSSOP 4.4mm M8.173
8 Ld TSSOP 4.4mm M8.173 Pb-free

X4323S8-2.7A X4323 AN
Ordering Information Continued

PART NUMBER RESET

ACTIVE LOW

PART MARKING

RESET

PART VCC RANGE VTRIP RANGE TEMP.

ACTIVE HIGH MARKING

RANGE °C

PACKAGE

PKG. DWG. #

X4323V8-4.5A 4323 AL

X4325V8-4.5A 4325 AL
0 to 70 8 Ld TSSOP 4.4mm M8.173

X4323V8Z-4.5A 4323 ALZ Note

X4325V8Z-4.5A 4325 ALZ Note
0 to 70 8 Ld TSSOP 4.4mm M8.173 Pb-free

X4323V8I-4.5A 4323 AM

X4325V8I-4.5A 4325 AM
-40 to 85 8 Ld TSSOP 4.4mm M8.173

X4323V8IZ-4.5A 4323 AMZ Note

X4325V8IZ-4.5A 4325 AMZ Note
-40 to 85 8 Ld TSSOP 4.4mm M8.173 Pb-free

NOTE Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8122.1

May 25, 2006

X4323, X4325

PRINCIPLES OF OPERATION

Power-on Reset Application of power to the X4323, X4325 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits.

It prevents the system microprocessor from starting to operate with insufficient voltage.

It prevents the processor from operating prior to stabilization of the oscillator.

It allows time for an FPGA to download its configuration prior to initialization of the circuit.

It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up.

When VCC exceeds the device VTRIP threshold value for 200ms nominal the circuit releases RESET/RESET allowing the system to begin operation.

LOW VOLTAGE MONITORING

During operation, the X4323, X4325 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms.

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to

LOW periodically, while SCL is HIGH this is a start bit prior to the expiration of the watchdog time out period to prevent a RESET/RESET signal. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH.

EEPROM INADVERTENT WRITE PROTECTION

When RESET/RESET goes active as a result of a low voltage condition or Watchdog Timer Time Out, any inprogress communications are terminated. While RESET/RESET is active, no new communications are allowed and no nonvolatile write operation can start. Nonvolatile writes in-progress when RESET/RESET goes active are allowed to finish.

Additional protection mechanisms are provided with memory Block Lock and the Write Protect WP pin. These are discussed elsewhere in this document.

More datasheets: X4323S8I | X4323S8 | X4325V8I-2.7A | X4325S8I | X4325S8I-2.7A | X4325S8I-4.5A | X4325V8 | X4323V8-4.5A | X4325S8-2.7A | X4323V8-2.7A

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived X4325S8-4.5A Datasheet file may be downloaded here without warranties.

Datasheet ID: X4325S8-4.5A 639235