ISL62884CHRTZ-T

ISL62884CHRTZ-T Datasheet

ISL62884C

Part	Datasheet
ISL62884CHRTZ-T	ISL62884CHRTZ-T (pdf)

Related Parts	Information
ISL62884CIRTZ-T	ISL62884CIRTZ-T
ISL62884CHRTZ	ISL62884CHRTZ
ISL62884CIRTZ	ISL62884CIRTZ

PDF Datasheet Preview
ISL62884C Single-Phase PWM Regulator for IMVP-6 Mobile CPUs ISL62884C The ISL62884C is a single-phase PWM buck regulator for miroprocessor core power supply. It uses an integrated gate drivers to provide a complete solution. The PWM modulator of ISL62884C is based on Intersil's Robust Ripple Regulator R3 technology. Compared with traditional modulators, the R3 modulator commands variable switching frequency during load transients, achieving faster transient response. With the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. The ISL62884C is fully compliant with IMVP-6 specifications. It responds to DPRSLPVR signals by entering/exiting diode emulation mode. It reports the regulator output current through the IMON pin. It senses the current by using either discrete resistor or inductor DCR whose variation over-temperature can be thermally compensated by a single NTC thermistor. It uses differential remote voltage sensing to accurately regulate the processor die voltage. The adaptive body diode conduction time reduction function minimizes the body diode conduction loss in diode emulation mode. User-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress. • Precision Core Voltage Regulation - System Accuracy Over-Temperature - Enhanced Load Line Accuracy • Voltage Identification Input - 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps - Supports VID Changes On-The-Fly • Supports Multiple Current Sensing Methods - Lossless Inductor DCR Current Sensing - Precision Resistor Current Sensing • Superior Noise Immunity and Transient Response • Current Monitor • Differential Remote Voltage Sensing • High Efficiency Across Entire Load Range • Integrated Gate Driver • Adaptive Body Diode Conduction Time Reduction • User-selectable Overshoot Reduction Function • Small Footprint 28 Ld 4x4 TQFN Package • Pb-Free RoHS Compliant Applications* see page 29 • Notebook Core Voltage Regulator • Notebook GPU Voltage Regulator Related Literature* see page 29 • See AN1545 for Evaluation Board Application Note “ISL62884CEVAL2Z Evaluation User Guide” Load Line Regulation VOUT V VIN = 19V VIN = 12V VIN = 8V 2 4 6 8 10 12 14 16 18 20 22 IOUT A March 16, 2010 FN7591.0 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 \| Intersil and design is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL62884C Ordering Information PART NUMBER Notes 1, 2, 3 PART MARKING TEMP. RANGE °C PACKAGE Pb-Free PKG. DWG. # ISL62884CHRTZ 62884C HRTZ -10 to +100 28 Ld 4x4 TQFN L28.4x4 ISL62884CIRTZ 62884C IRTZ -40 to +100 28 Ld 4x4 TQFN L28.4x4 Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations . Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. For Moisture Sensitivity Level MSL , please see device information page for ISL62884C. For more information on MSL please see techbrief TB363. Pin Configuration ISL62884C 28 LD TQFN TOP VIEW DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 28 27 26 25 24 23 22 CLK_EN# 1 PGOOD 2 RBIAS 3 VW 4 COMP 5 FB 6 VSEN 7 PD BOTTOM 21 VID1 20 VID0 19 VCCP 18 LGATE 17 VSSP 16 PHASE 15 UGATE 8 9 10 11 12 13 14 RTN ISUMISUM+ VDD VIN DPRSTP# BOOT FN7591.0 March 16, 2010 ISL62884C Pin Function Description PIN NUMBER 1 2 3 4 5 6 7 8 9, 10 11 12 13 14 15 16 17 18 19 20 thru 26 27 28 CLK_EN# PGOOD Open drain output to enable system PLL clock. It goes low 13 switching cycles after VCORE is within 10% of VBOOT. Power-Good open-drain output indicating when the regulator is able to supply regulated voltage. Pull-up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V. Ordering Information 2 Pin Configuration 2 Pin Function Description 3 Block Diagram 4 Absolute Maximum Ratings 6 Thermal Information 6 Recommended Operating Conditions 6 Electrical Specifiactions 6 Gate Driver Timing Diagram 9 Simplified Application Circuits 9 Theory of Operation 11 Multiphase R3 Modulator 11 Diode Emulation and Period Stretching 12 Start-Up Timing 12 Voltage Regulation and Load Line Implementation 12 Differential Sensing 15 CCM Switching Frequency 15 Modes of Operation 15 Dynamic Operation 15 Protections 15 Adaptive Body Diode Conduction Time Reduction 16 Overshoot Reduction Function 16 Key Component Selection 17 RBIAS 17 Inductor DCR Current-Sensing Network 17 Resistor Current-Sensing Network 19 Overcurrent Protection 19 Load Line Slope 20 Compensator 20 Optional Slew Rate Compensation Circuit For 1-Tick VID Transition 21 Layout Guidelines 22 Reference Design Bill of Materials 25 Typical Performance 26 Products 29 Package Outline Drawing 30 FN7591.0 March 16, 2010 ISL62884C Absolute Maximum Ratings Supply Voltage, VDD. .-0.3V to +7V Battery Voltage, VIN +28V Boot Voltage BOOT -0.3V to +33V Boot to Phase Voltage BOOT-PHASE -0.3V to +7V DC -0.3V to +9V <10ns Phase Voltage PHASE -7V <20ns Pulse Width, 10µJ UGATE Voltage UGATE PHASE-0.3V DC to BOOT PHASE-5V <20ns Pulse Width, 10µJ to BOOT LGATE, LGATEa and LGATEb Voltage -0.3V DC to VDD+0.3V LGATEa and LGATEb -2.5V <20ns Pulse Width, 2.5µJ to VDD+0.3V LGATE -2.5V <20ns Pulse Width, 5µJ to VDD + 0.3V All Other Pins. -0.3V to VDD + 0.3V Open Drain Outputs, PGOOD, VR_TT#, CLK_EN# .-0.3V to +7V ESD Rating Human Body Model Tested per JESD22-A114E 2kV Machine Model Tested per JESD22-A115-A 200V Latch Up per JESD-78B Class 2, Level B, Note 6 100mA Thermal Information Thermal Resistance Typical °C/W °C/W 28 Ld TQFN Package Notes 4, 5 Maximum Junction Temperature +150°C Maximum Storage Temperature Range -65°C to +150°C Pb-Free Reflow Profile .see link below Recommended Operating Conditions Supply Voltage, VDD +5V ±5% Battery Voltage, VIN +4.5V to 25V Ambient Temperature ISL62884CHRTZ. -10°C to +100°C ISL62884CIRTZ -40°C to +100°C Junction Temperature ISL62884CHRTZ. -10°C to +125°C ISL62884CIRTZ -40°C to +125°C CAUTION Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. For the “case temp” location is the center of the exposed metal pad on the package underside. Jedec Class II pulse conditions and failure criterion uses. Level B exception is using a minimum negative pulse of -1.2V on the DPRSLPVR pin Electrical Specifications

PDF Datasheet Preview

ISL62884C

Single-Phase PWM Regulator for IMVP-6 Mobile CPUs

ISL62884C

The ISL62884C is a single-phase PWM buck regulator for miroprocessor core power supply. It uses an integrated gate drivers to provide a complete solution. The PWM modulator of ISL62884C is based on Intersil's Robust Ripple Regulator R3 technology. Compared with traditional modulators, the R3 modulator commands variable switching frequency during load transients, achieving faster transient response. With the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency.

The ISL62884C is fully compliant with IMVP-6 specifications. It responds to DPRSLPVR signals by entering/exiting diode emulation mode. It reports the regulator output current through the IMON pin. It senses the current by using either discrete resistor or inductor DCR whose variation over-temperature can be thermally compensated by a single NTC thermistor. It uses differential remote voltage sensing to accurately regulate the processor die voltage. The adaptive body diode conduction time reduction function minimizes the body diode conduction loss in diode emulation mode. User-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress.
• Precision Core Voltage Regulation - System Accuracy Over-Temperature - Enhanced Load Line Accuracy
• Voltage Identification Input - 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps - Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods - Lossless Inductor DCR Current Sensing - Precision Resistor Current Sensing
• Superior Noise Immunity and Transient Response
• Current Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Integrated Gate Driver
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 28 Ld 4x4 TQFN Package
• Pb-Free RoHS Compliant

Applications* see page 29
• Notebook Core Voltage Regulator
• Notebook GPU Voltage Regulator

Related Literature* see page 29
• See AN1545 for Evaluation Board Application Note “ISL62884CEVAL2Z Evaluation User Guide”

Load Line Regulation

VOUT V

VIN = 19V

VIN = 12V

VIN = 8V
2 4 6 8 10 12 14 16 18 20 22 IOUT A

March 16, 2010 FN7591.0

CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil and design is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ISL62884C
Ordering Information

PART NUMBER Notes 1, 2, 3

PART MARKING

TEMP. RANGE °C

PACKAGE Pb-Free

PKG. DWG. #

ISL62884CHRTZ
62884C HRTZ
-10 to +100
28 Ld 4x4 TQFN

L28.4x4

ISL62884CIRTZ
62884C IRTZ
-40 to +100
28 Ld 4x4 TQFN

L28.4x4

Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations . Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

For Moisture Sensitivity Level MSL , please see device information page for ISL62884C. For more information on MSL please see techbrief TB363.

Pin Configuration

ISL62884C 28 LD TQFN

TOP VIEW

DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2
28 27 26 25 24 23 22

CLK_EN# 1 PGOOD 2 RBIAS 3 VW 4 COMP 5 FB 6 VSEN 7

PD BOTTOM
21 VID1 20 VID0 19 VCCP 18 LGATE 17 VSSP 16 PHASE 15 UGATE
8 9 10 11 12 13 14

RTN ISUMISUM+

VDD VIN DPRSTP# BOOT

FN7591.0

March 16, 2010

ISL62884C

Pin Function Description

PIN NUMBER
1 2 3 4 5 6 7 8 9, 10 11 12 13 14
15 16 17
18 19 20 thru 26 27 28

CLK_EN# PGOOD

Open drain output to enable system PLL clock. It goes low 13 switching cycles after VCORE is within 10% of VBOOT.

Power-Good open-drain output indicating when the regulator is able to supply regulated voltage. Pull-up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
Ordering Information 2

Pin Configuration 2

Pin Function Description 3

Block Diagram 4

Absolute Maximum Ratings 6

Thermal Information 6

Recommended Operating Conditions 6

Electrical Specifiactions 6

Gate Driver Timing Diagram 9

Simplified Application Circuits 9

Theory of Operation 11 Multiphase R3 Modulator 11 Diode Emulation and Period Stretching 12 Start-Up Timing 12 Voltage Regulation and Load Line Implementation 12 Differential Sensing 15 CCM Switching Frequency 15 Modes of Operation 15 Dynamic Operation 15 Protections 15 Adaptive Body Diode Conduction Time Reduction 16 Overshoot Reduction Function 16

Key Component Selection 17 RBIAS 17 Inductor DCR Current-Sensing Network 17 Resistor Current-Sensing Network 19 Overcurrent Protection 19 Load Line Slope 20 Compensator 20 Optional Slew Rate Compensation Circuit For 1-Tick VID Transition 21

Layout Guidelines 22

Reference Design Bill of Materials 25

Typical Performance 26

Products 29

Package Outline Drawing 30

FN7591.0

March 16, 2010

ISL62884C

Absolute Maximum Ratings

Supply Voltage, VDD. .-0.3V to +7V Battery Voltage, VIN +28V Boot Voltage BOOT -0.3V to +33V Boot to Phase Voltage BOOT-PHASE -0.3V to +7V DC
-0.3V to +9V <10ns Phase Voltage PHASE -7V <20ns Pulse Width, 10µJ UGATE Voltage UGATE PHASE-0.3V DC to BOOT

PHASE-5V <20ns Pulse Width, 10µJ to BOOT LGATE, LGATEa and LGATEb Voltage -0.3V DC to VDD+0.3V LGATEa and LGATEb -2.5V <20ns Pulse Width, 2.5µJ to VDD+0.3V LGATE -2.5V <20ns Pulse Width, 5µJ to VDD + 0.3V All Other Pins. -0.3V to VDD + 0.3V Open Drain Outputs, PGOOD, VR_TT#, CLK_EN#
.-0.3V to +7V ESD Rating

Human Body Model Tested per JESD22-A114E 2kV Machine Model Tested per JESD22-A115-A 200V Latch Up per JESD-78B Class 2, Level B, Note 6 100mA

Thermal Information

Thermal Resistance Typical
°C/W °C/W
28 Ld TQFN Package Notes 4, 5

Maximum Junction Temperature +150°C

Maximum Storage Temperature Range -65°C to +150°C

Pb-Free Reflow Profile .see link below

Recommended Operating Conditions

Supply Voltage, VDD +5V ±5% Battery Voltage, VIN +4.5V to 25V Ambient Temperature

ISL62884CHRTZ. -10°C to +100°C ISL62884CIRTZ -40°C to +100°C Junction Temperature ISL62884CHRTZ. -10°C to +125°C ISL62884CIRTZ -40°C to +125°C

CAUTION Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379.

For the “case temp” location is the center of the exposed metal pad on the package underside. Jedec Class II pulse conditions and failure criterion uses. Level B exception is using a minimum negative pulse of -1.2V on the

DPRSLPVR pin

Electrical Specifications

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ISL62884CHRTZ-T Datasheet file may be downloaded here without warranties.

Datasheet ID: ISL62884CHRTZ-T 639175